Improving FPGA Performance for Carry-Save Arithmetic.

Hadi Parandeh-Afshar Ajay K. Verma Philip Brisk Paolo Ienne

Published in: IEEE Trans. Very Large Scale Integr. Syst. (2010)

Keyphrases

hardware implementation
pipelined architecture
low cost
real time
high speed
neural network
information retrieval
website
evolutionary algorithm
wireless sensor networks
hardware architecture
digital signal