Ajay K. Verma

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 13

Top Topics

Wavelet Features

Brain Computer Interface

Top Venues

Publications

Chunwu Wang, Ajay K. Verma, Shubha Majumder, Xin Xiong, Chunling Liu, Bijay Guragain
Power Spectrum Characteristics of EEG Channels during Awake and REM Sleep Stages for Bruxism Patients. ISAIMS (2023)
Chunwu Wang, Ajay K. Verma, Sergio D. Cabrera, Jau-Shin Lou
Long-Term Effects of Ischemic Stroke on Autonomic Regulation. IEEE Access 9 (2021)
Chunwu Wang, Bijay Guragain, Ajay K. Verma, Lewis Archer, Shubha Majumder, Abdiaziz Mohamud, Emily Flaherty-Woods, Geoffrey Shapiro, Mahathir Almashor, Mike Lenné, Rama Myers, Jonny Kuo, Shiyan Yang, Nicholas Wilson, Kouhyar Tavakolian
Spectral Analysis of EEG During Microsleep Events Annotated via Driver Monitoring System to Characterize Drowsiness. IEEE Trans. Aerosp. Electron. Syst. 56 (2) (2020)
Nicholas Wilson, Bijay Guragain, Ajay K. Verma, Lewis Archer, Kouhyar Tavakolian
Blending Human and Machine: Feasibility of Measuring Fatigue Through the Aviation Headset. Hum. Factors 62 (4) (2020)
Bijay Guragain, Ali Bahrami Rad, Chunwu Wang, Ajay K. Verma, Lewis Archer, Nicholas Wilson, Kouhyar Tavakolian
EEG-based Classification of Microsleep by Means of Feature Selection: An Application in Aviation. EMBC (2019)
Shabaz Khan, Chunwu Wang, Kouhyar Tavakolian, Ajay K. Verma
Early Identification of Bleeding: Past Achievement, Current Limitations & Future Development. EIT (2018)
Kasper Sørensen, Ajay K. Verma, Andrew P. Blaber, John M. Zanetti, Samuel Emil Schmidt, Johannes J. Struijk, Kouhyar Tavakolian
Challenges in Using Seismocardiography for Blood Pressure Monitoring. CinC (2017)
Nasim Alamdari, Ali Haider, M. Riadh Arefin, Ajay K. Verma, Kouhyar Tavakolian, Reza Fazel-Rezai
A review of methods and applications of brain computer interface systems. EIT (2016)
Tamanna Tabassum Khan Munia, Kouhyar Tavakolian, Ajay K. Verma, Vahid Zakeri, Farzad Khosrow-Khavar, Reza Fazel-Rezai, Alireza Akhbardeh
Heart Sound Classification from Wavelet Decomposed Signal Using Morphological and Statistical Features. CinC (2016)
Tamanna T. K. Munia, Jeffrey L. Gendreau, Ajay K. Verma, Benjamin D. Johnson, Mark Romanick, Kouhyar Tavakolian, Reza Fazel-Rezai
Preliminary results of residual deficits observed in athletes with concussion history: Combined EEG and cognitive study. EMBC (2016)
Ajay K. Verma, Amanmeet Garg, Andrew P. Blaber, Reza Fazel-Rezai, Kouhyar Tavakolian
Analysis of causal cardio-postural interaction under orthostatic stress using convergent cross mapping. EMBC (2016)
Nandu Goswami, Ajay K. Verma, Amanmeet Garg, Da Xu, Reza Fazel-Rezai, Kouhyar Tavakolian, Andrew P. Blaber
Increased Systolic Blood Pressure driven Skeletal Muscle activation Following Stroke: A causality analysis. CinC (2016)
Ajay K. Verma, Amanmeet Garg, Andrew P. Blaber, Reza Fazel-Rezai, Kouhyar Tavakolian
Causality detection in cardio-postural interaction under orthostatic stress induced by quiet standing using transfer entropy. EIT (2016)
Ajay K. Verma, Reza Fazel-Rezai, Andrew P. Blaber, Kouhyar Tavakolian
Pulse Transit Time Extraction from Seismocardiogram and its Relationship with Pulse Pressure. CinC (2015)
Ajay K. Verma, Amanmeet Garg, Andrew P. Blaber, Reza Fazel-Rezai, Kouhyar Tavakolian
Causality in the Cardio-Postural Interactions During Quiet Stance. CinC (2015)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (3) (2010)
Amit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL (2010)
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18 (4) (2010)
Philip Brisk, Ajay K. Verma, Paolo Ienne
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic (2009)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD (2009)
Philip Brisk, Ajay K. Verma, Paolo Ienne
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. 13 (1-2) (2009)
Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne
Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC (2009)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
Arithmetic optimization for custom instruction set synthesis. SASP (2009)
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA (2008)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (10) (2008)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE (2008)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC (2008)
Ajay K. Verma, Paolo Ienne
Automatic synthesis of compressor trees: reevaluating large counters. DATE (2007)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC (2007)
Ajay K. Verma, Paolo Ienne
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. ASP-DAC (2007)
Philip Brisk, Ajay K. Verma, Paolo Ienne
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD (2007)
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
Enhancing FPGA Performance for Arithmetic Circuits. DAC (2007)
Ajay K. Verma, Philip Brisk, Paolo Ienne
Rethinking custom ISE identification: a new processor-agnostic method. CASES (2007)
Philip Brisk, Ajay K. Verma, Paolo Ienne
An optimistic and conservative register assignment heuristic for chordal graphs. CASES (2007)
Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE (2006)
Ajay K. Verma, Paolo Ienne
Towards the automatic exploration of arithmetic-circuit architectures. DAC (2006)
Paolo Ienne, Ajay K. Verma
Arithmetic Transformations to Maximise the Use of Compressor Trees. DELTA (2004)
Ajay K. Verma, Paolo Ienne
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. ICCAD (2004)