Enhancing FPGA Performance for Arithmetic Circuits.
Philip BriskAjay K. VermaPaolo IenneHadi Parandeh-AfsharPublished in: DAC (2007)
Keyphrases
- high speed
- pipelined architecture
- power reduction
- hardware implementation
- real time image processing
- low power
- high level synthesis
- low cost
- field programmable gate array
- parallel hardware
- digital circuits
- real time
- fpga implementation
- shift register
- delay insensitive
- vlsi circuits
- genetic algorithm
- lateral inhibition
- digital signal
- dedicated hardware
- arithmetic operations
- hardware design
- floating point