Laura Pozzi

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 33

Top Topics

Design Space Exploration

Signal Analysis

High Level Synthesis

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda Calero, David Atienza, Laura Pozzi
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. CoRR (2024)
Riccardo Felici, Laura Pozzi, Carlo A. Furia
HyperPUT: generating synthetic faulty programs to challenge bug-finding tools. Empir. Softw. Eng. 29 (2) (2024)
Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi
Graph Neural Networks for High-Level Synthesis Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures. DATE (2023)
Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. DSN-W (2023)
Cristian Tirelli, Lorenzo Ferretti, Laura Pozzi
SAT-MapIt: An Open Source Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures. CF (2023)
Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing. CF (2023)
Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi
A Parametrizable Template for Approximate Logic Synthesis. DSN-W (2023)
Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection. DATE (2022)
Riccardo Felici, Laura Pozzi, Carlo A. Furia
HyperPUT: Generating Synthetic Faulty Programs to Challenge Bug-Finding Tools. CoRR (2022)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. CoRR (2021)
Lorenzo Ferretti, Andrea Cini, Georgios Zacharopoulos, Cesare Alippi, Laura Pozzi
A Graph Deep Learning Framework for High-Level Synthesis Design Space Exploration. CoRR (2021)
João M. P. Cardoso, André DeHon, Laura Pozzi
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems. IEEE Trans. Computers 70 (12) (2021)
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. IEEE Embed. Syst. Lett. 13 (4) (2021)
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. IEEE Trans. Emerg. Top. Comput. 9 (1) (2021)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
Approximate Logic Synthesis: A Survey. Proc. IEEE 108 (12) (2020)
Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. ARC (2020)
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)
Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code. ICCD (2019)
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. DATE (2019)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC (2019)
Loris Duch, Soumya Basu, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. IEEE Embed. Syst. Lett. 11 (2) (2019)
Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
Circuit carving: A methodology for the design of approximate hardware. DATE (2018)
Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. HPCS (2018)
Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
A partitioning strategy for exploring error-resilience in circuits: work-in-progress. CASES (2018)
Soumya Basu, Loris Duch, Miguel Peón Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. ISCAS (2018)
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
Lattice-Traversing Design Space Exploration for High Level Synthesis. ICCD (2018)
Soumya Basu, Loris Duch, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Loris Duch, Soumya Basu, Rubén Braojos, David Atienza, Giovanni Ansaloni, Laura Pozzi
A multi-core reconfigurable architecture for ultra-low power bio-signal analysis. BioCAS (2016)
Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza
Inexact-aware architecture design for ultra-low power bio-signal analysis. IET Comput. Digit. Tech. 10 (6) (2016)
Emanuele Giaquinta, Anadi Mishra, Laura Pozzi
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (3) (2015)
Emanuele Giaquinta, Laura Pozzi
An Effective Exact Algorithm and a New Upper Bound for the Number of Contacts in the Hydrophobic-Polar Two-Dimensional Lattice Model. J. Comput. Biol. 20 (8) (2013)
Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
EGRA: A Coarse Grained Reconfigurable Architectural Template. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE (2011)
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. DATE (2009)
Alex Orailoglu, Laura Pozzi
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (12) (2009)
Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. 4 (2009)
Paolo Bonzini, Laura Pozzi
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 16 (10) (2008)
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
Compiling custom instructions onto expression-grained reconfigurable architectures. CASES (2008)
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. SASP (2008)
Laura Pozzi, Pierre G. Paulin
A future of customizable processors: are we there yet? DATE (2007)
Paolo Bonzini, Laura Pozzi
Polynomial-time subgraph enumeration for automated instruction set extension. DATE (2007)
Paolo Bonzini, Laura Pozzi
A Retargetable Framework for Automated Discovery of Custom Instructions. ASAP (2007)
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement CoRR (2007)
Paolo Bonzini, Dilek Harmanci, Laura Pozzi
A Study of Energy Saving in Customizable Processors. SAMOS (2007)
Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS (2007)
Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
Introduction of Architecturally Visible Storage in Instruction Set Extensions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Miljan Vuletic, Laura Pozzi, Paolo Ienne
Virtual memory window for application-specific reconfigurable coprocessors. IEEE Trans. Very Large Scale Integr. Syst. 14 (8) (2006)
Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. DATE (2006)
Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
Automatic identification of application-specific functional units with architecturally visible storage. DATE (2006)
Paolo Bonzini, Laura Pozzi
Code transformation strategies for extensible embedded processors. CASES (2006)
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. Very Large Scale Integr. Syst. 14 (7) (2006)
Laura Pozzi, Kubilay Atasu, Paolo Ienne
Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (7) (2006)
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. VLSI Design (2006)
André DeHon, Yury Markovsky, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
Stream computations organized for reconfigurable execution. Microprocess. Microsystems 30 (6) (2006)
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. DATE (2005)
Laura Pozzi, Paolo Ienne
Exploiting pipelining to relax register-file port constraints of instruction-set extensions. CASES (2005)
Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. CODES+ISSS (2005)
Miljan Vuletic, Laura Pozzi, Paolo Ienne
Seamless Hardware-Software Integration in Reconfigurable Computing Systems. IEEE Des. Test Comput. 22 (2) (2005)
Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. DATE (2004)
Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES (2004)
Miljan Vuletic, Laura Pozzi, Paolo Ienne
Virtual memory window for application-specific reconfigurable coprocessors. DAC (2004)
Miljan Vuletic, Laura Pozzi, Paolo Ienne
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. FPL (2004)
Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt
Introduction of local memory elements in instruction set extensions. DAC (2004)
Miljan Vuletic, Laura Pozzi, Paolo Ienne
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. ASAP (2004)
Miljan Vuletic, Laura Pozzi, Paolo Ienne
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. FCCM (2004)
Kubilay Atasu, Laura Pozzi, Paolo Ienne
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. 31 (6) (2003)
Kubilay Atasu, Laura Pozzi, Paolo Ienne
Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC (2003)
Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
Automatic Instruction Set Extension and Utilization for Embedded Processors. ASAP (2003)
Laura Pozzi, Miljan Vuletic, Paolo Ienne
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. DATE (2002)
Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
Determining the Optimum Extended Instruction-Set Architecture for Application Specific Reconfigurable VLIW CPUs. IEEE International Workshop on Rapid System Prototyping (2001)
Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract). FPGA (2000)
Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami
A DAG-Based Design Approach for Reconfigurable VLIW Processors. DATE (1999)
Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami
Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract). FPGA (1998)
Fabrizio Ferrandi, Franco Fummi, Laura Pozzi, Mariagiovanna Sami
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays. DFT (1997)