Giovanni Ansaloni

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 54

Top Topics

Signal Analysis

Design Space Exploration

Reconfigurable Architecture

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Alireza Amirshahi, Giovanni Ansaloni, David Atienza
Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures. PARMA-DITAM (2024)
Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32 (6) (2024)
Corey Lammie, Flavio Ponzina, Yuxuan Wang, Joshua Klein, Marina Zapater, Irem Boybat, Abu Sebastian, Giovanni Ansaloni, David Atienza
LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles. CoRR (2024)
Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda Calero, David Atienza, Laura Pozzi
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. CoRR (2024)
Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE (2024)
Rubén Rodríguez Álvarez, Benoît W. Denkinger, Juan Sapriza, José Miranda Calero, Giovanni Ansaloni, David Atienza Alonso
An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing. CF (2023)
Michael T. Niemier, X. S. Hu, L. Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan, Daniel C. Ralph
Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. DATE (2023)
Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. IEEE Trans. Computers 72 (7) (2023)
Alireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, David Atienza
TiC-SAT: Tightly-Coupled Systolic Accelerator for Transformers. ASP-DAC (2023)
Rafael Medina, Joshua Kein, Giovanni Ansaloni, Marina Zapater, Sergi Abadal, Eduard Alarcón, David Atienza
System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms. ASP-DAC (2023)
Silvio Zanoli, Giovanni Ansaloni, Tomás Teijeiro, David Atienza
Event-based sampled ECG morphology reconstruction through self-similarity. Comput. Methods Programs Biomed. 240 (2023)
Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Alireza Amirshahi, Giovanni Ansaloni, David Atienza
Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures. CoRR (2023)
Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. 11 (2) (2023)
Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Miroslav Vasic, David Atienza
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC (2023)
Rafael Medina, Darong Huang, Giovanni Ansaloni, Marina Zapater, David Atienza
REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal. VLSI-SoC (2023)
Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection. DATE (2022)
Pengbo Yu, Alexandre Levisse, Mohit Gupta, Timon Evenblij, Giovanni Ansaloni, Francky Catthoor, David Atienza
A Soft SIMD Based Energy Efficient Computing Microarchitecture. CoRR (2022)
Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza
A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro 42 (6) (2022)
Rafael Medina, Joshua Kein, Yasir Mahmood Qureshi, Marina Zapater, Giovanni Ansaloni, David Atienza
Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures. LASCAS (2022)
Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR (2022)
Flavio Ponzina, Miguel Peón Quirós, Giovanni Ansaloni, David Atienza
An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs. COINS (2022)
Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning. CoRR (2022)
Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. ACM Great Lakes Symposium on VLSI (2022)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI (2022)
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE (2021)
Joshua Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max C. Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF (2021)
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. CoRR (2021)
William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC (2021)
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. IEEE Embed. Syst. Lett. 13 (4) (2021)
Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI (2021)
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. IEEE Trans. Emerg. Top. Comput. 9 (1) (2021)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda
Approximate Logic Synthesis: A Survey. Proc. IEEE 108 (12) (2020)
Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. ARC (2020)
Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)
Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code. ICCD (2019)
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. DATE (2019)
Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC (2019)
Loris Duch, Soumya Basu, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. IEEE Embed. Syst. Lett. 11 (2) (2019)
Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
Circuit carving: A methodology for the design of approximate hardware. DATE (2018)
Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. HPCS (2018)
Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi
A partitioning strategy for exploring error-resilience in circuits: work-in-progress. CASES (2018)
Soumya Basu, Loris Duch, Miguel Peón Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. ISCAS (2018)
Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi
Lattice-Traversing Design Space Exploration for High Level Synthesis. ICCD (2018)
Rubén Braojos, Daniele Bortolotti, Andrea Bartolini, Giovanni Ansaloni, Luca Benini, David Atienza
A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing. IEEE Trans. Computers 66 (4) (2017)
Soumya Basu, Loris Duch, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza
HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Loris Duch, Soumya Basu, Rubén Braojos, David Atienza, Giovanni Ansaloni, Laura Pozzi
A multi-core reconfigurable architecture for ultra-low power bio-signal analysis. BioCAS (2016)
Daniele Bortolotti, Andrea Bartolini, Luca Benini, V. Rajesh Pamula, Nick Van Helleputte, Chris Van Hoof, Marian Verhelst, Tobias Gemmeke, Rubén Braojos Lopez, Giovanni Ansaloni, David Atienza, Pierre Vandergheynst
PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms. Conf. Computing Frontiers (2016)
Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni
Nano-engineered architectures for ultra-low power wireless body sensor nodes. CODES+ISSS (2016)
Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza
Inexact-aware architecture design for ultra-low power bio-signal analysis. IET Comput. Digit. Tech. 10 (6) (2016)
Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, David Atienza
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices. ISVLSI (2015)
Rubén Braojos, Ahmed Yasir Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza
Hardware/software approach for code synchronization in low-power multi-core sensor nodes. DATE (2014)
Hossein Mamaghanian, Giovanni Ansaloni, David Atienza, Pierre Vandergheynst
Power-efficient joint compressed sensing of multi-lead ECG signals. ICASSP (2014)
Frédéric Giroud, Pascal Persechini, Pierre-François Ruedi, Giovanni Ansaloni, Rubén Braojos, F. Viemon, Frederic Masson
Live demonstration: ECG sensor interface in a low power SoC for wireless portable ECG monitoring. BioCAS (2014)
Jelena Milosevic, Andreas Dittrich, Alberto Ferrante, Miroslaw Malek, Camilo Rojas Quiros, Rubén Braojos, Giovanni Ansaloni, David Atienza
Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach. CinC (2014)
Rubén Braojos, Ivan Beretta, Giovanni Ansaloni, David Atienza
Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes. Sensors 14 (12) (2014)
Rubén Braojos, Hossein Mamaghanian, Alair Dias Junior, Giovanni Ansaloni, David Atienza, Francisco J. Rincón, Srinivasan Murali
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems. DAC (2014)
Rubén Braojos, Giovanni Ansaloni, David Atienza
A methodology for embedded classification of heartbeats using random projections. DATE (2013)
Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. DATE (2013)
Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (12) (2012)
Marios Milis, Kyriacos Michaelides, Anastasis Kounoudes, Giovanni Ansaloni, David Atienza, Frédéric Giroud, Pierre-François Ruedi, Frederic Masson
IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities). BIBE (2012)
Rubén Braojos, Giovanni Ansaloni, David Atienza, Francisco J. Rincón
Embedded real-time ECG delineation methods: A comparative evaluation. BIBE (2012)
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
EGRA: A Coarse Grained Reconfigurable Architectural Template. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE (2011)
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. DATE (2009)
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
Compiling custom instructions onto expression-grained reconfigurable architectures. CASES (2008)
Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. SASP (2008)