Guilhem Larrieu

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 9

Top Topics

Mathematical Analysis

Top Venues

Publications

Yifan Wang, Chhandak Mukherjee, Houssem Rezgui, Marina Deng, Cristell Maneux, Sara Mannaa, Ian O'Connor, Jonas Müller, Sylvain Pelloquin, Guilhem Larrieu
Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design. ESSDERC (2023)
Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar
A Logic Cell Design and routing Methodology Specific to VNWFET. NEWCAS (2022)
Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. VLSI-SoC (2022)
Arnaud Poittevin, Chhandak Mukherjee, Ian O'Connor, Cristell Maneux, Guilhem Larrieu, Marina Deng, Sébastien Le Beux, François Marc, Aurélie Lecestre, Cédric Marchand, Abhishek Kumar
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SoC (Selected Papers) (2020)
Chhandak Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Cédric Marchand, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SOC (2020)
C. Mukherjee, Marina Deng, François Marc, Cristell Maneux, Arnaud Poittevin, Ian O'Connor, Sébastien Le Beux, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu
3D logic cells design and results based on Vertical NWFET technology including tied compact model. CoRR (2020)
Peter R. Wiecha, Aurélie Lecestre, Nicolas Mallet, Guilhem Larrieu
Pushing the limits of optical information storage using deep learning. CoRR (2018)
Chhandak Mukherjee, Cristell Maneux, Julien Pezard, Guilhem Larrieu
1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors. ESSDERC (2017)
Guilhem Larrieu, Y. Guerfi, X. L. Han, N. Clement
Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array. ESSDERC (2015)