Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
Lucas RéveilChhandak MukherjeeCristell ManeuxMarina DengFrançois MarcAbhishek KumarAurélie LecestreGuilhem LarrieuArnaud PoittevinIan O'ConnorOskar BaumgartnerDavid PirkerPublished in: VLSI-SoC (2022)