3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Arnaud PoittevinChhandak MukherjeeIan O'ConnorCristell ManeuxGuilhem LarrieuMarina DengSébastien Le BeuxFrançois MarcAurélie LecestreCédric MarchandAbhishek KumarPublished in: VLSI-SoC (Selected Papers) (2020)