Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array.

Guilhem Larrieu Y. Guerfi X. L. Han N. Clement

Published in: ESSDERC (2015)

Keyphrases

field effect transistors
leakage current
high density
steady state
metal oxide
mathematical analysis
schottky barrier
gate dielectrics
low voltage
programmable logic
linear array
random access memory
chemical vapor deposition
case study
si sio
optimal solution