Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.
Yifan WangChhandak MukherjeeHoussem RezguiMarina DengCristell ManeuxSara MannaaIan O'ConnorJonas MüllerSylvain PelloquinGuilhem LarrieuPublished in: ESSDERC (2023)