Marco Rios

Publication Activity (10 Years)

Years Active: 2019-2023
Publications (10 Years): 14

Top Topics

Memory Hierarchy

Top Venues

ACM Trans. Embed. Comput. Syst.

Publications

Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. 11 (2) (2023)
Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC (2023)
Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza
A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro 42 (6) (2022)
Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR (2022)
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI (2022)
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE (2021)
Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI (2021)
Alexandre Levisse, Marco Rios, Miguel Peón Quirós, David Atienza
Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. ICASSP (2020)
Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. ASP-DAC (2020)
William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers 69 (9) (2020)
Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access 8 (2020)
Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC (2019)
Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS (2019)