Alexandre Levisse

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 41

Top Topics

Energy Efficient

Top Venues

ACM Great Lakes Symposium on VLSI

IEEE Trans. Computers

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32 (6) (2024)
Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR (2024)
Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. IEEE Trans. Computers 72 (7) (2023)
Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max C. Lemme, Joshua Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors. IEEE Wirel. Commun. 30 (4) (2023)
Silvio Zanoli, Flavio Ponzina, Tomás Teijeiro, Alexandre Levisse, David Atienza
An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (2) (2023)
Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. 11 (2) (2023)
Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Miroslav Vasic, David Atienza
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Pengbo Yu, Alexandre Levisse, Mohit Gupta, Timon Evenblij, Giovanni Ansaloni, Francky Catthoor, David Atienza
A Soft SIMD Based Energy Efficient Computing Microarchitecture. CoRR (2022)
Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza
A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro 42 (6) (2022)
Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR (2022)
Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza
ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning. CoRR (2022)
Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. ACM Great Lakes Symposium on VLSI (2022)
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI (2022)
Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE (2021)
Joshua Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max C. Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF (2021)
William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC (2021)
Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI (2021)
Sergi Abadal, Robert Guirado, Hamidreza Taghvaee, Akshay Jain, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed Elsayed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max C. Lemme, Joshua Klein, Marina Zapater, Alexandre Levisse, David Atienza, Davide Rossi, Francesco Conti, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors. CoRR (2020)
Halima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza
Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters. ISVLSI (2020)
Alexandre Levisse, Marco Rios, Miguel Peón Quirós, David Atienza
Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. ICASSP (2020)
Halima Najibi, Alexandre Levisse, Marina Zapater, Mohamed M. Sabry Aly, David Atienza
Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology. ACM Great Lakes Symposium on VLSI (2020)
Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza
RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. ASP-DAC (2020)
William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. VLSI-SOC (2020)
William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers 69 (9) (2020)
Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access 8 (2020)
Loris Duch, Miguel Peón Quirós, Pieter Weckx, Alexandre Levisse, Rubén Braojos, Francky Catthoor, David Atienza
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors. IEEE Trans. Very Large Scale Integr. Syst. 28 (10) (2020)
Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC (2019)
Deepak M. Mathew, André Lucas Chinazzo, Christian Weis, Matthias Jung, Bastien Giraud, Pascal Vivet, Alexandre Levisse, Norbert Wehn
RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. SAMOS (2019)
William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza
BLADE: A BitLine Accelerator for Devices on the Edge. ACM Great Lakes Symposium on VLSI (2019)
Mouhamad Alayan, Eloi Muhr, Alexandre Levisse, Marc Bocquet, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, Jean-Michel Portal
Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory Arrays. IEEE Trans. Circuits Syst. II Express Briefs (5) (2019)
Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS (2019)
William Andrew Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza
A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture. DAC (2019)
Halima Najibi, Alexandre Levisse, Marina Zapater
A Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with Integrated Flow Cell Arrays. ISLPED (2019)
Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations. DCIS (2018)
Gilbert Sassine, Cecile Nail, Luc Tillie, Diego Alfaro Robayo, Alexandre Levisse, Carlo Cagli, Khalil El Hajjam, Jean-Francois Nodin, Elisa Vianello, Mathieu Bernard, Gabriel Molas, Etienne Nowak
Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications. IRPS (2018)
Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS (2017)
Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
Architecture, design and technology guidelines for crosspoint memories. NANOARCH (2017)
Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
High density emerging resistive memories: What are the limits? LASCAS (2017)
Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal
Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. NANOARCH (2016)
Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal
SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. NVMTS (2015)
S. Ben Krit, Wenceslas Rahajandraibe, Karine Castellani-Coulié, Gilles Micolau, Alexandre Levisse, A. Lyoussi
Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination. LATW (2014)