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Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes.
Michele Caon
Clément Choné
Pasquale Davide Schiavone
Alexandre Levisse
Guido Masera
Maurizio Martina
David Atienza
Published in:
CoRR (2024)
Keyphrases
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digital signal processors
weighted graph
disjoint paths
edge detection
low memory
memory space
directed graph
limited memory
undirected graph
computing power
general purpose
memory usage
memory requirements
shortest path
low cost
edge information
neural network