A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication.
Grégoire EggermannMarco RiosGiovanni AnsaloniSani R. NassifDavid AtienzaPublished in: VLSI-SoC (2023)
Keyphrases
- floating point
- sparse matrix
- low power
- power consumption
- vlsi architecture
- instruction set
- floating point arithmetic
- high speed
- nm technology
- low cost
- cmos technology
- fixed point
- mixed signal
- digital signal processing
- analog to digital converter
- power reduction
- real time
- power dissipation
- image sensor
- random access memory
- pattern recognition