Madhura Purnaprajna

ORCID

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 13

Top Venues

VLSI Design

FCCM

FPL

ACM Trans. Embed. Comput. Syst.

University of Paderborn (PHD)

Education History

University of Paderborn

PHD

Publications

Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders. IEEE Des. Test 40 (1) (2023)
M. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication. VLSID (2022)
Oscar Ferraz, Srinivasan Subramaniyan, Ramesh Chinthalaa, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. IEEE Commun. Surv. Tutorials 24 (1) (2022)
Remya Ramakrishnan, Aditya K. V. Dev, Darshik A. S, Renuka Chinchwadkar, Madhura Purnaprajna
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis. VLSI Design (2021)
Sagar Eetha, Sruthi P. K., Vibha Panty, Sahu Sai Vikram, Mihir Mody, Madhura Purnaprajna
TileNET: Hardware accelerator for ternary Convolutional Neural Networks. Microprocess. Microsystems 83 (2021)
Nesma M. Rezk, Madhura Purnaprajna, Tomas Nordström, Zain Ul-Abdin
Recurrent Neural Networks: An Embedded Computing Perspective. IEEE Access 8 (2020)
Oscar Ferraz, Srinivasan Subramaniyan, Guohui Wang, Joseph R. Cavallaro, Gabriel Falcão, Madhura Purnaprajna
Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications. FCCM (2020)
Srinivasan Subramaniyan, Oscar Ferraz, M. R. Ashuthosh, Santosh Krishna, Guohui Wang, Joseph R. Cavallaro, Vítor Silva, Gabriel Falcão, Madhura Purnaprajna
Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs. SiPS (2020)
Simmi M. Bose, Varsha S. Lalapura, S. Saravanan, Madhura Purnaprajna
k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics. VLSI Design (2019)
Nesma M. Rezk, Madhura Purnaprajna, Tomas Nordström, Zain Ul-Abdin
Recurrent Neural Networks: An Embedded Computing Perspective. CoRR (2019)
Nesma M. Rezk, Madhura Purnaprajna, Zain Ul-Abdin
Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures. IPDPS Workshops (2018)
Sahu Sai Vikram, Vibha Panty, Mihir Mody, Madhura Purnaprajna
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs. VLSI Design (2018)
Vanishree K, Madhura Purnaprajna
Performance modeling for data distribution in heterogeneous computing systems: work in progress. CASES (2018)
Muhsen Owaida, Gabriel Falcão, João Andrade, Christos D. Antonopoulos, Nikolaos Bellas, Madhura Purnaprajna, David Novo, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. ACM Trans. Embed. Comput. Syst. 14 (2) (2015)
Meena Belwal, Madhura Purnaprajna, T. S. B. Sudarshan
Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions. FPL (2015)
Madhura Purnaprajna, Paolo Ienne
A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. FCCM (2013)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA (2013)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow And-Inverter Cones. FPL (2013)
Madhura Purnaprajna, Paolo Ienne
Making wide-issue VLIW processors viable on FPGAs. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Gabriel Falcão, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. FCCM (2012)
Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert, Michael Hussmann, Michael Thies, Uwe Kastens
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis. ACM Trans. Reconfigurable Technol. Syst. 3 (3) (2010)
Madhura Purnaprajna, Mario Porrmann, Ulrich Rückert
Run-time reconfigurability in embedded multiprocessors. SIGARCH Comput. Archit. News 37 (2) (2009)
Madhura Purnaprajna, Christopher Pohl, Mario Porrmann, Ulrich Rückert
Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing. ERSA (2009)
Mario Porrmann, Madhura Purnaprajna, Christoph Puttmann
Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance. AHS (2009)
Madhura Purnaprajna, Christoph Puttmann, Mario Porrmann
Power Aware Reconfigurable Multiprocessor for Elliptic Curve Cryptography. DATE (2008)
Madhura Purnaprajna, Marek Reformat, Witold Pedrycz
Genetic algorithms for hardware-software partitioning and optimal resource allocation. J. Syst. Archit. 53 (7) (2007)
Madhura Purnaprajna, Marek Reformat, Witold Pedrycz
Genetic Algorithms in Hardware-Software Partitioning. ERSA (2004)

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Publication Activity (10 Years)

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Madhura Purnaprajna