Grace Zgheib

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 11

Top Topics

Design Parameters

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Stefan Nikolic, Grace Zgheib, Paolo Ienne
Detailed Placement for Dedicated LUT-Level FPGA Interconnect. ACM Trans. Reconfigurable Technol. Syst. 15 (4) (2022)
Grace Zgheib, Yu Shen Lu, Ilya Ganusov
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. FPL (2021)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. FPL (2020)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. FPGA (2020)
Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov
Architectural Enhancements in Intel® Agilex™ FPGAs. FPGA (2020)
Stefan Nikolic, Grace Zgheib, Paolo Ienne
Finding a Needle in the Haystack of Hardened Interconnect Patterns. FPL (2019)
Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI (2017)
Grace Zgheib, Paolo Ienne
Evaluating FPGA clusters under wide ranges of design parameters. FPL (2017)
Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. FPGA (2017)
Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. FPGA (2016)
Grace Zgheib, Paolo Ienne
Automatic wire modeling to explore novel FPGA architectures. FPT (2016)
Haidar M. Harmanani, Danielle Azar, Grace Zgheib, David Kozhaya
An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components. IRI (2015)
Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne
Improved carry chain mapping for the VTR flow. FPT (2015)
Grace Zgheib, Iyad Ouaiss
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations. J. Circuits Syst. Comput. 24 (3) (2015)
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne
A technology mapper for depth-constrained FPGA logic cells. FPL (2015)
Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne
Revisiting and-inverter cones. FPGA (2014)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). FPGA (2013)
Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne
Shadow And-Inverter Cones. FPL (2013)
Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA (2011)