Colin Yu Lin

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 4

Top Topics

Design Space Exploration

Tensor Decomposition

Hardware Implementation

Top Venues

SIGARCH Comput. Archit. News

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Weiyun Jiang, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (9) (2021)
Weiyun Jiang, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform. CoRR (2020)
Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44 (4) (2016)
Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen, Xin-Gang Wang, Zhenhong Guo
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (8) (2016)
Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne
A technology mapper for depth-constrained FPGA logic cells. FPL (2015)
Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang
Exploring architecture parameters for dual-output LUT based FPGAs. FPL (2014)
Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang
A survey of open source processors for FPGAs. FPL (2014)
Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang
Size aware placement for island style FPGAs. FPT (2014)
Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin
A semi-supervised modeling approach for performance characterization of FPGA architectures. FPL (2014)
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Design space exploration for sparse matrix-matrix multiplication on FPGAs. Int. J. Circuit Theory Appl. 41 (2) (2013)
Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. FCCM (2013)
Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang
Timing-constrained minimum area/power FPGA memory mapping. FPL (2013)
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). FPGA (2012)
Colin Yu Lin, Hayden Kwok-Hay So
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. SIGARCH Comput. Archit. News 40 (5) (2012)
Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong
A Model for Matrix Multiplication Performance on FPGAs. FPL (2011)
Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong
A Model for Peak Matrix Performance on FPGAs. FCCM (2011)
Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So
Design space exploration for sparse matrix-matrix multiplication on FPGAs. FPT (2010)
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Operation scheduling for FPGA-based reconfigurable computers. FPL (2009)
Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan
A Network Based Functional Verification Method of IEEE 1394a PHY Core. ISVLSI (2008)