Hayden Kwok-Hay So

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 73

Top Venues

Publications

Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. CoRR (2024)
Jiajun Zhou, Jiajun Wu, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference. CoRR (2023)
Jiajun Wu, Jiajun Zhou, Yizhao Gao, Yuhao Ding, Ngai Wong, Hayden Kwok-Hay So
MSD: Mixing Signed Digit Representations for Hardware-efficient DNN Acceleration on FPGA with Heterogeneous Resources. FCCM (2023)
Yizhao Gao, Song Wang, Hayden Kwok-Hay So
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Mo Song, Jiajun Wu, Yuhao Ding, Hayden Kwok-Hay So
SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks. ICFPT (2023)
Zhenyu Wu, Mo Song, Hayden Kwok-Hay So
Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision. ICFPT (2023)
Song Wang, Zhu Wang, Can Li, Xiaojuan Qi, Hayden Kwok-Hay So
SpikeMOT: Event-based Multi-Object Tracking with Sparse Motion Features. CoRR (2023)
Maolin Wang, Ian McInerney, Bartolomeo Stellato, Stephen P. Boyd, Hayden Kwok-Hay So
RSQP: Problem-specific Architectural Customization for Accelerated Convex Quadratic Optimization. ISCA (2023)
Yizhao Gao, Baoheng Zhang, Xiaojuan Qi, Hayden Kwok-Hay So
DPACS: Hardware Accelerated Dynamic Neural Network Pruning through Algorithm-Architecture Co-design. ASPLOS (2) (2023)
Yuhao Ding, Jiajun Wu, Yizhao Gao, Maolin Wang, Hayden Kwok-Hay So
Model-Platform Optimized Deep Neural Network Accelerator Generation through Mixed-Integer Geometric Programming. FCCM (2023)
Yizhao Gao, Song Wang, Hayden Kwok-Hay So
REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs. FPGA (2022)
Maolin Wang, Seyedramin Rasoulinezhad, Philip H. W. Leong, Hayden Kwok-Hay So
NITI: Training Integer Neural Networks Using Integer-Only Arithmetic. IEEE Trans. Parallel Distributed Syst. 33 (11) (2022)
Maolin Wang, Kelvin C. M. Lee, Bob M. F. Chung, Sharatchandra Varma Bogaraju, Ho-Cheung Ng, Justin S. J. Wong, Ho Cheung Shum, Kevin K. Tsia, Hayden Kwok-Hay So
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. IEEE Trans. Neural Networks Learn. Syst. 33 (7) (2022)
Junjie Liu, Zhe Xu, Runbin Shi, Ray C. C. Cheung, Hayden Kwok-Hay So
Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. ICLR (2020)
Cyrus Wing-Hei Chan, Philip H. W. Leong, Hayden Kwok-Hay So
Vision Guided Crop Detection in Field Robots using FPGA-Based Reconfigurable Computers. ISCAS (2020)
Runbin Shi, Peiyan Dong, Tong Geng, Yuhao Ding, Xiaolong Ma, Hayden Kwok-Hay So, Martin C. Herbordt, Ang Li, Yanzhi Wang
CSB-RNN: A Faster-than-Realtime RNN Acceleration Framework with Compressed Structured Blocks. CoRR (2020)
Junjie Liu, Zhe Xu, Runbin Shi, Ray C. C. Cheung, Hayden Kwok-Hay So
Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers. CoRR (2020)
Maolin Wang, SeyedRamin Rasoulinezhad, Philip H. W. Leong, Hayden Kwok-Hay So
NITI: Training Integer Neural Networks Using Integer-only Arithmetic. CoRR (2020)
Sung-En Chang, Yanyu Li, Mengshu Sun, Runbin Shi, Hayden Kwok-Hay So, Xuehai Qian, Yanzhi Wang, Xue Lin
Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework. CoRR (2020)
Runbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding
FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. DAC (2020)
Runbin Shi, Yuhao Ding, Xuechao Wei, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding
FTDL: An FPGA-tailored Architecture for Deep Learning Systems. FPGA (2020)
Runbin Shi, Peiyan Dong, Tong Geng, Yuhao Ding, Xiaolong Ma, Hayden Kwok-Hay So, Martin C. Herbordt, Ang Li, Yanzhi Wang
CSB-RNN: a faster-than-realtime RNN acceleration framework with compressed structured blocks. ICS (2020)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access 7 (2019)
Runbin Shi, Justin S. J. Wong, Hayden Kwok-Hay So
High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing. J. Imaging 5 (3) (2019)
Nina Engelhardt, Hayden Kwok-Hay So
GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms. CoRR (2019)
Runbin Shi, Junjie Liu, Hayden Kwok-Hay So, Shuo Wang, Yun Liang
E-LSTM: Efficient Inference of Sparse LSTM on Embedded Heterogeneous System. DAC (2019)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Design of quadruple precision multiplier architectures with SIMD single and double precision support. Integr. 65 (2019)
Nan Meng, Hayden Kwok-Hay So, Xing Sun, Edmund Y. Lam
High-dimensional Dense Residual Convolutional Neural Network for Light Field Reconstruction. CoRR (2019)
Zhenbo Ren, Hayden Kwok-Hay So, Edmund Y. Lam
Fringe Pattern Improvement and Super-Resolution Using Deep Learning in Digital Holography. IEEE Trans. Ind. Informatics 15 (11) (2019)
Runbin Shi, Justin S. J. Wong, Edmund Y. Lam, Kevin K. Tsia, Hayden Kwok-Hay So
A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy. IEEE Trans. Biomed. Circuits Syst. 13 (4) (2019)
Nina Engelhardt, Hayden Kwok-Hay So
GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms. ACM Trans. Reconfigurable Technol. Syst. 12 (4) (2019)
Nan Meng, Edmund Y. Lam, Kevin K. Tsia, Hayden Kwok-Hay So
Large-Scale Multi-Class Image-Based Cell Classification With Deep Learning. IEEE J. Biomed. Health Informatics 23 (5) (2019)
Nan Meng, Xing Sun, Hayden Kwok-Hay So, Edmund Y. Lam
Computational Light Field Generation Using Deep Nonparametric Bayesian Learning. IEEE Access 7 (2019)
Wei Zhao, Jian-Qiang Lin, S. C. Chan, Hayden Kwok-Hay So
A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization. IEEE Access 6 (2018)
Vincent W. L. Tam, Chunkit Chui, Hayden Kwok-Hay So, Nyein Thwe Khaing, Andy Chung To Kong, Subhayan Roy
Urban Farming in Myanmar: An Experiential Learning Project for Engineering and Science Students from Hong Kong and Myanmar. TALE (2018)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Universal number posit arithmetic generator on FPGA. DATE (2018)
Nina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So
Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems. FPL (2018)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS (2018)
Hayden Kwok-Hay So, Warren J. Gross
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 90 (1) (2018)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. Circuits Syst. Signal Process. 37 (1) (2018)
Nina Engelhardt, Hayden Kwok-Hay So
Towards Flexible Automatic Generation of Graph Processing Gateware. HEART (2017)
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10 (2) (2017)
Hayden Kwok-Hay So, John Wawrzynek
Proceedings of the 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017). CoRR (2017)
Hayden Kwok-Hay So, John Wawrzynek
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. FPGA (2017)
Xing Sun, Nelson H. C. Yung, Edmund Y. Lam, Hayden Kwok-Hay So
Computationally Efficient Hyperspectral Data Learning Based on the Doubly Stochastic Dirichlet Process. IEEE Trans. Geosci. Remote. Sens. 55 (1) (2017)
Justin S. J. Wong, Runbin Shi, Maolin Wang, Hayden Kwok-Hay So
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory. FPT (2017)
Sam M. H. Ho, Hayden Kwok-Hay So
NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs. FPT (2017)
Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So
A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. FCCM (2017)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Nan Meng, Hayden Kwok-Hay So, Edmund Y. Lam
Computational single-cell classification using deep learning on bright-field and phase images. MVA (2017)
Nina Engelhardt, Hayden Kwok-Hay So
GraVF: A vertex-centric distributed graph processing framework on FPGAs. FPL (2016)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision division architecture. MWSCAS (2016)
Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. SIGARCH Comput. Archit. News 44 (4) (2016)
Hayden Kwok-Hay So, John Wawrzynek
Proceedings of the 2nd International Workshop on Overlay Architectures for FPGAs (OLAF 2016). CoRR (2016)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. ISVLSI (2016)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture for quadruple precision floating point division with multi-precision support. ASAP (2016)
Xing Sun, Nan Meng, Zhimin Xu, Edmund Y. Lam, Hayden Kwok-Hay So
Sparse Hierarchical Nonparametric Bayesian learning for light field representation and denoising. IJCNN (2016)
Xing Sun, Zhimin Xu, Nan Meng, Edmund Y. Lam, Hayden Kwok-Hay So
Data-driven light field depth estimation using deep Convolutional Neural Networks. IJCNN (2016)
Nina Engelhardt, Hayden Kwok-Hay So
Vertex-Centric Graph Processing on FPGA. FCCM (2016)
Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig (2016)
Hayden Kwok-Hay So, John Wawrzynek
OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. FPGA (2016)
Xing Sun, Nelson H. C. Yung, Edmund Y. Lam, Hayden Kwok-Hay So
Consistency Analysis for the Doubly Stochastic Dirichlet Process. CoRR (2016)
Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT (2016)
Ho-Cheung Ng, Cheng Liu, Hayden Kwok-Hay So
A Soft Processor Overlay with Tightly-coupled FPGA Accelerator. CoRR (2016)
Sam M. H. Ho, Maolin Wang, Ho-Cheung Ng, Hayden Kwok-Hay So
Towards FPGA-assisted spark: An SVM training acceleration case study. ReConFig (2016)
Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So
Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay. CoRR (2015)
Cheng Liu, Ho-Cheung Ng, Hayden Kwok-Hay So
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay. FPT (2015)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC (2015)
Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Cheng Liu, Hayden Kwok-Hay So
Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. FCCM (2015)
Junyi Xie, Xinyu Niu, Andy K. S. Lau, Kevin K. Tsia, Hayden Kwok-Hay So
Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy. FPT (2015)
Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI (2015)
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
Significant papers from the first 25 years of the FPL conference. FPL (2015)
Brandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So
Mixed-architecture process scheduling on tightly coupled reconfigurable computers. FPL (2014)
Brandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So
Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers. FCCM (2014)
Yuk-Ming Choi, Hayden Kwok-Hay So
Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster. ASAP (2014)
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Design space exploration for sparse matrix-matrix multiplication on FPGAs. Int. J. Circuit Theory Appl. 41 (2) (2013)
Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So
A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. FCCM (2013)
Ho-Cheung Ng, Yuk-Ming Choi, Hayden Kwok-Hay So
Direct virtual memory access from FPGA for high-productivity heterogeneous computing. FPT (2013)
Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So
Extending BORPH for shared memory reconfigurable computers. FPL (2012)
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). FPGA (2012)
Junying Chen, Alfred C. H. Yu, Hayden Kwok-Hay So
Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU. FPT (2012)
Colin Yu Lin, Hayden Kwok-Hay So
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. SIGARCH Comput. Archit. News 40 (5) (2012)
Hayden Kwok-Hay So, Junying Chen, Billy Y. S. Yiu, Alfred C. H. Yu
Medical Ultrasound Imaging: To GPU or Not to GPU? IEEE Micro 31 (5) (2011)
Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong
A Model for Matrix Multiplication Performance on FPGAs. FPL (2011)
Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong
A Model for Peak Matrix Performance on FPGAs. FCCM (2011)
Junying Chen, Billy Y. S. Yiu, Brandon Kyle Hamilton, Alfred C. H. Yu, Hayden Kwok-Hay So
Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging. SIGARCH Comput. Archit. News 39 (4) (2011)
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng
On IIR-based bit-stream multipliers. Int. J. Circuit Theory Appl. 39 (2) (2011)
Sammy H. M. Kwok, Hayden Kwok-Hay So, Edmund Y. Lam, King-Shan Lui
Zero-configuration identity-based IP network encryptor. IEEE Trans. Consumer Electron. 56 (2) (2010)
Chi Chiu Tsang, Hayden Kwok-Hay So
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation. SIGARCH Comput. Archit. News 38 (4) (2010)
Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So
Design space exploration for sparse matrix-matrix multiplication on FPGAs. FPT (2010)
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
Operation scheduling for FPGA-based reconfigurable computers. FPL (2009)
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng
Direct sigma-delta modulated signal processing in FPGA. FPL (2008)
Hayden Kwok-Hay So, Robert W. Brodersen
Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPH. FCCM (2008)
Hayden Kwok-Hay So, Robert W. Brodersen
File system access from reconfigurable FPGA hardware processes in BORPH. FPL (2008)
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng
Quad-level bit-stream signal processing on FPGAs. FPT (2008)
Hayden Kwok-Hay So, Robert W. Brodersen
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. ACM Trans. Embed. Comput. Syst. 7 (2) (2008)
Dejan Markovic, Chen Chang, Brian C. Richards, Hayden Kwok-Hay So, Borivoje Nikolic, Robert W. Brodersen
ASIC Design and Verification in an FPGA Environment. CICC (2007)
Hayden Kwok-Hay So, Robert W. Brodersen
Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support. FPL (2006)
Hayden Kwok-Hay So, Artem Tkachenko, Robert W. Brodersen
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH. CODES+ISSS (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hayden Kwok-Hay So