Mei Wen

ORCID

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 61

Top Venues

Publications

Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen
ESEN: Efficient GPU sharing of Ensemble Neural Networks. Neurocomputing 599 (2024)
Jing Feng, Mei Wen, Xin Ju, Junzhong Shen, Yang Guo
Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. ISCAS (2024)
Zeyu Xue, Mei Wen, Zhaoyun Chen, Yang Shi, Minjin Tang, Jianchao Yang, Zhongdi Luo
Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format. ICCD (2023)
Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang
Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs. DAC (2023)
Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. ICCD (2022)
Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang
S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. ISCAS (2022)
Jianchao Yang, Mei Wen, Xiaolei Zhao, Yang Shi
. ICC (2022)
Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. CoRR (2022)
Can Deng, Zhaoyun Chen, Yang Shi, Xichang Kong, Mei Wen
Exploring ILP for VLIW Architecture by Quantified Modeling and Dynamic Programming-Based Instruction Scheduling. ASP-DAC (2022)
Jianan Wang, Yang Shi, Zhaoyun Chen, Mei Wen
CORF: Bridging the Gap of Complex Operator Fusion for Faster DNN Inference. HPCC/DSS/SmartCity/DependSys (2022)
Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys (2022)
Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. ISPASS (2022)
Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP (2022)
Yang Shi, Mei Wen
sRouting: Towards a Better Flow Size Estimation Performance through Routing and Sketch Configuration. ICPP (2021)
Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li
Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. HPCC/DSS/SmartCity/DependSys (2021)
Xiaolei Zhao, Mei Wen, Zhaoyun Chen, Yang Shi, Chunyuan Zhang
Automatic mapping and code optimization for OpenCL kernels on FT-matrix architecture (WIP paper). LCTES (2021)
Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang
SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. HPCC/DSS/SmartCity/DependSys (2021)
Minghua He, Jialiang Qin, Mei Wen, Wenbei Chen
Sustaining Consumer Trust and Continuance Intention by Institutional Mechanisms: An Empirical Survey of DiDi in China. IEEE Access 9 (2021)
Yang Shi, Mei Wen, Chunyuan Zhang
Incremental Deployment of Programmable Switches for Sketch-based Network Measurement. ISCC (2020)
Zhaoyun Chen, Dafei Huang, Lei Luo, Mei Wen, Chunyuan Zhang
Efficient Parallel TLD on CPU-GPU Platform for Real-Time Tracking. KSII Trans. Internet Inf. Syst. 14 (1) (2020)
Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA (2020)
Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. DAC (2020)
Junzhong Shen, You Huang, Mei Wen, Chunyuan Zhang
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang
Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. ICA3PP (1) (2020)
Yang Shi, Mei Wen, Chunyuan Zhang
Towards High-Efficiency Data Centers via Job-Aware Network Scheduling. ICPP (2020)
Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang
Optimized HybridSketch: More Efficient with Analysis and Algorithm. ICA3PP (1) (2020)
Zhaoyun Chen, Wei Quan, Mei Wen, Jianbin Fang, Jie Yu, Chunyuan Zhang, Lei Luo
Deep Learning Research and Development Platform: Characterizing and Scheduling with QoS Guarantees on GPU Clusters. IEEE Trans. Parallel Distributed Syst. 31 (1) (2020)
Xiaolei Zhao, Mei Wen, Minjin Tang, Qun Huang, Chunyuan Zhang
HybridSketch: A Memory-centric Precise Approach for Flow Measurement. ICC (2020)
Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. IEEE Access 8 (2020)
Zhaoyun Chen, Lei Luo, Haoduo Yang, Jie Yu, Mei Wen, Chunyuan Zhang
GENIE: QoS-guided Dynamic Scheduling for CNN-based Tasks on SME Clusters. DATE (2019)
Zhuang Cao, Huiguo Zhang, Junnan Li, Mei Wen, Chunyuan Zhang
A Fast Approach for Generating Efficient Parsers on FPGAs. Symmetry 11 (10) (2019)
Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang
KVSwitch: An In-network Load Balancer for Key-Value Stores. ISCC (2019)
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. ISCAS (2019)
Zijun Hang, Yang Shi, Mei Wen, Wei Quan, Chunyuan Zhang
SWAP: a sliding window algorithm for in-network packet measurement. HP3C (2019)
Zijun Hang, Mei Wen, Yang Shi, Chunyuan Zhang
Interleaved Sketch: Toward Consistent Network Telemetry for Commodity Programmable Switches. IEEE Access 7 (2019)
Yang Shi, Jiawei Fei, Mei Wen, Chunyuan Zhang
Application-Oriented Network Scheduling With Metaflow. IEEE Access 7 (2019)
Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. FPGA (2019)
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. ICPP (2019)
Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. DAC (2019)
Jiawei Fei, Yang Shi, Qun Huang, Mei Wen
Metaflow: A DAG-Based Network Abstraction for Distributed Applications. CoRR (2019)
Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang
Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. INFOCOM Workshops (2019)
Jiawei Fei, Yang Shi, Mei Wen, Chunyuan Zhang
SACC: Configuring Application-Level Cache Intelligently for In-Memory Database Based on Long Short-Term Memory. HPCC/SmartCity/DSS (2019)
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. CoRR (2019)
Zijun Hang, Yang Shi, Mei Wen, Chunyuan Zhang
TBSW: Time-Based Sliding Window Algorithm for Network Traffic Measurement. HPCC/SmartCity/DSS (2019)
Zhaoyun Chen, Lei Luo, Wei Quan, Mei Wen, Chunyuan Zhang
Poster Abstract: Deep Learning Workloads Scheduling with Reinforcement Learning on GPU Clusters. INFOCOM Workshops (2019)
Yang Shi, Jiawei Fei, Mei Wen, Qun Huang, Nan Wu
Metaflow: A Better Traffic Abstraction for Distributed Applications. HPCC/SmartCity/DSS (2019)
Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. CoRR (2018)
You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. IEICE Electron. Express 15 (10) (2018)
Haoduo Yang, Huayou Su, Qiang Lan, Mei Wen, Chunyuan Zhang
High performance graph analytics with productivity on hybrid CPU-GPU platforms. HP3C (2018)
Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. FPGA (2018)
Haoduo Yang, Huayou Su, Qiang Lan, Mei Wen, Chunyuan Zhang
HPGraph: High-Performance Graph Analytics with Productivity on the GPU. Sci. Program. 2018 (2018)
Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. ISCAS (2018)
Zhaoyun Chen, Lei Luo, Wei Quan, Yang Shi, Jie Yu, Mei Wen, Chunyuan Zhang
Multiple CNN-based Tasks Scheduling across Shared GPU Platform in Research and Development Scenarios. HPCC/SmartCity/DSS (2018)
Yanpeng Wang, Mei Wen, Chunyuan Zhang, Jie Lin
RVNet: A fast and high energy efficiency network packet processing system on RISC-V. ASAP (2017)
Dafei Huang, Lei Luo, Zhaoyun Chen, Mei Wen, Chunyuan Zhang
Applying Detection Proposals to Visual Tracking for Scale and Aspect Ratio Adaptability. Int. J. Comput. Vis. 122 (3) (2017)
Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC (2017)
Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29 (20) (2017)
Yun-gang Xue, Huayou Su, Ju Ren, Mei Wen, Chunyuan Zhang, Li-quan Xiao
A Highly Parallel and Scalable Motion Estimation Algorithm with GPU for HEVC. Sci. Program. 2017 (2017)
Qiang Lan, Zelong Wang, Mei Wen, Chunyuan Zhang, Yijie Wang
High Performance Implementation of 3D Convolutional Neural Networks on a GPU. Comput. Intell. Neurosci. 2017 (2017)
Zhaoyun Chen, Lei Luo, Dafei Huang, Mei Wen, Chunyuan Zhang
Exploiting a depth context model in visual tracking with correlation filter. Frontiers Inf. Technol. Electron. Eng. 18 (5) (2017)
Johannes Langguth, Qiang Lan, Namit Gaur, Xing Cai, Mei Wen, Chunyuan Zhang
Enabling Tissue-Scale Cardiac Simulations Using Heterogeneous Computing on Tianhe-2. ICPADS (2016)
Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang
Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. IEICE Trans. Inf. Syst. (4) (2015)
Dafei Huang, Lei Luo, Mei Wen, Zhaoyun Chen, Chunyuan Zhang
Enable Scale and Aspect Ratio Adaptability in Visual Tracking with Detection Proposals. BMVC (2015)
Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) (2015)
Huayou Su, Xing Cai, Mei Wen, Chunyuan Zhang
An analytical GPU performance model for 3D stencil computations from the angle of data traffic. J. Supercomput. 71 (7) (2015)
Zhaoyun Chen, Lei Luo, Mei Wen, Chunyuan Zhang
Fast tracking via context depth model learning. ICIP (2015)
Jun Chai, Johan Hake, Nan Wu, Mei Wen, Xing Cai, Glenn Terje Lines, Jing Yang, Huayou Su, Chunyuan Zhang, Xiangke Liao
Towards simulation of subcellular calcium dynamics at nanometre resolution. Int. J. High Perform. Comput. Appl. 29 (1) (2015)
Mei Wen, Dafei Huang, Changqing Xun, Dong Chen
Improving performance portability for GPU-specific OpenCL kernels on multi-core/many-core CPUs by analysis-based transformations. Frontiers Inf. Technol. Electron. Eng. 16 (11) (2015)
Xinnan Dong, Mei Wen, Jun Chai, Xing Cai, Mandan Zhao, Chunyuan Zhang
Communication-hiding programming for clusters with multi-coprocessor nodes. Concurr. Comput. Pract. Exp. 27 (16) (2015)
Xinnan Dong, Jun Chai, Jing Yang, Mei Wen, Nan Wu, Xing Cai, Chunyuan Zhang, Zhaoyun Chen
Utilizing Multiple Xeon Phi Coprocessors on One Compute Node. ICA3PP (2) (2014)
Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang
High efficient sedimentary basin simulations on hybrid CPU-GPU clusters. Clust. Comput. 17 (2) (2014)
Dafei Huang, Mei Wen, Changqing Xun, Dong Chen, Xing Cai, Yuran Qiao, Nan Wu, Chunyuan Zhang
Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs. Euro-Par (2014)
Jun Chai, Huayou Su, Mei Wen, Xing Cai, Nan Wu, Chunyuan Zhang
Resource-efficient utilization of CPU/GPU-based heterogeneous supercomputers for Bayesian phylogenetic inference. J. Supercomput. 66 (1) (2013)
Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
On the GPU Performance of 3D Stencil Computations Implemented in OpenCL. ISC (2013)
Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai, Chunyuan Zhang, Qianming Yang
Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. IEICE Trans. Inf. Syst. (12) (2013)
Dong Chen, Changqing Xun, Dafei Huang, Mei Wen, Chunyuan Zhang
Automatic Mapping Single-Device OpenCL Program to Heterogeneous Multi-device Platform. HPCC/EUC (2013)
Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
On the GPU-CPU Performance Portability of OpenCL for 3D Stencil Computations. ICPADS (2013)
Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. J. Supercomput. 63 (2) (2013)
Huayou Su, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai
Performance of Sediment Transport Simulations on NVIDIA's Kepler Architecture. ICCS (2013)
Jing Yang, Jun Chai, Mei Wen, Nan Wu, Chunyuan Zhang
Solving the Cardiac Model Using Multi-core CPU and Many Integrated Cores (MIC). HPCC/EUC (2013)
Nan Wu, Yuran Qiao, Mei Wen, Chunyuan Zhang
ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit. APPT (2013)
Changqing Xun, Mei Wen, Nan Wu, Chunyuan Zhang, Hayden Kwok-Hay So
Extending BORPH for shared memory reconfigurable computers. FPL (2012)
Huayou Su, Jun Chai, Mei Wen, Ju Ren, Chunyuan Zhang
Parallelization Design of Irregular Algorithms of Video Processing on GPUs. ICME (2012)
Qiang Lan, Changqing Xun, Mei Wen, Huayou Su, Lifang Liu, Chunyuan Zhang
Improving Performance of GPU Specific OpenCL Program on CPUs. PDCAT (2012)
Nan Wu, Mei Wen, Huayou Su, Ju Ren, Chunyuan Zhang
A Parallel H.264 Encoder with CUDA: Mapping and Evaluation. ICPADS (2012)
Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao
The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). FPGA (2012)
Mei Wen, Huayou Su, Wenjie Wei, Nan Wu, Xing Cai, Chunyuan Zhang
Using 1000+ GPUs and 10000+ CPUs for Sedimentary Basin Simulations. CLUSTER (2012)
Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang
Tiled Multi-Core Stream Architecture. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren
A high-efficient software parallel CAVCL encoder based on GPU. TSP (2011)
Huayou Su, Nan Wu, Chunyuan Zhang, Mei Wen, Ju Ren
A Multilevel Parallel Intra Coding for H.264/AVC Based on CUDA. ICIG (2011)
Xiong Xiong, Mei Wen, Wei Zhang, Yongjie Zhang
Cross-Market Financial Risk Analysis: an Agent-Based Computational Finance. Int. J. Inf. Technol. Decis. Mak. 10 (3) (2011)
Huayou Su, Chunyuan Zhang, Jun Chai, Mei Wen, Nan Wu, Ju Ren
High-efficient software parallel CAVLC encoder based on programmable stream processor. ACM Multimedia (2011)
Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. DSD (2010)
Ju Ren, Mei Wen, Chunyuan Zhang, Huayou Su, Yi He, Nan Wu
A Parallel Streaming Motion Estimation for Real-Time HD H.264 Encoding on Programmable Processors. FCST (2010)
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang
SAT: A Stream Architecture Template for Embedded Applications. CIT (2010)
Ju Ren, Yi He, Wei Wu, Mei Wen, Nan Wu, Chunyuan Zhang
Software parallel CAVLC encoder based on stream processing. ESTIMedia (2009)
Nan Wu, Mei Wen, Ju Ren, Yi He, Changqing Xun, Wei Wu, Chunyuan Zhang
Cache streamization for high performance stream processor. HiPC (2009)
Nan Wu, Mei Wen, Wei Wu, Ju Ren, Huayou Su, Changqing Xun, Chunyuan Zhang
Streaming HD H.264 encoder on programmable processors. ACM Multimedia (2009)
Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang
Load scheduling: Reducing pressure on distributed register files for free. ASP-DAC (2008)
Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun
On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. IEEE Micro 28 (4) (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Mei Wen