Sheng Liu

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 15

Top Topics

Top Venues

CCF Trans. High Perform. Comput.

ACM Trans. Embed. Comput. Syst.

Publications

Lanting Guo, Haiyan Chen, Chen Li, Sheng Liu
LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access. ISCAS (2024)
Tiehang Duan, Zhenyi Wang, Sheng Liu, Yiyi Yin, Sargur N. Srihari
UNCER: A framework for uncertainty estimation and reduction in neural decoding of EEG signals. Neurocomputing 538 (2023)
Kai Lu, Yaohua Wang, Yang Guo, Chun Huang, Sheng Liu, Ruibo Wang, Jianbin Fang, Tao Tang, Zhaoyun Chen, Biwei Liu, Zhong Liu, Yuanwu Lei, Haiyan Sun
MT-3000: a heterogeneous multi-zone processor for HPC. CCF Trans. High Perform. Comput. 4 (2) (2022)
Tiehang Duan, Zhenyi Wang, Sheng Liu, Sargur N. Srihari, Hui Yang
Uncertainty Detection in EEG Neural Decoding Models. CoRR (2022)
Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys (2022)
Hongli Zhong, Zhong Liu, Sheng Liu, Sheng Ma, Chen Li
Adaptive Low-Cost Loop Expansion for Modulo Scheduling. NPC (2022)
Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP (2022)
Yaohua Wang, Chen Li, Chang Liu, Sheng Liu, Yuanwu Lei, Jian Zhang, Yang Zhang, Yang Guo
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions. CCF Trans. High Perform. Comput. 3 (1) (2021)
Rui Song, Guozhao Zeng, Sheng Liu, Haiyan Chen
Conflict-Free Block-with-Stride Access of 2D Storage Structure. ICA3PP (3) (2018)
Zerun Li, Yang Guo, Sheng Liu, Junyang Zhang
A task-based multi-core allocation mechanism for packet acceleration. IEICE Electron. Express 15 (12) (2018)
Hongbing Tan, Haiyan Chen, Sheng Liu, Jianguo Wu
Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures. ASAP (2017)
Xiaowen Chen, Zhonghai Lu, Sheng Liu, Shuming Chen
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Hongbing Tan, Haiyan Chen, Sheng Liu, Xikun Ma, Yaqing Chi
A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS. NCCET (2017)
Sheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. ISVLSI (2016)
Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. ISVLSI (2016)
Chao Yang, Haiyan Chen, Sheng Liu, Sheng Ma
A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension. NCCET (2015)
Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning
FT-Matrix: A Coordination-Aware Architecture for Signal Processing. IEEE Micro 34 (6) (2014)
Yaohua Wang, Shuming Chen, Hu Chen, Jianghua Wan, Kai Zhang, Sheng Liu
Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures. IEICE Trans. Inf. Syst. (2) (2013)
Wei Liu, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, Xi Ning
A novel QPP interleaver for parallel turbo decoder. IEICE Electron. Express 10 (8) (2013)
Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Hu Chen, Sheng Liu, Xi Ning
A cost conscious performance model for media processors. IEICE Electron. Express 9 (11) (2012)
Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu
Erratum: Control-enhanced power-SIMD [IEICE Electronics Express Vol.9 (2012), No 14 pp 1147-1152]. IEICE Electron. Express 9 (16) (2012)
Kai Zhang, Shuming Chen, Hu Chen, Yaohua Wang, Xiaowen Chen, Sheng Liu, Wei Liu
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors. IEICE Electron. Express 9 (4) (2012)
Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu
Control-enhanced power-SIMD. IEICE Electron. Express 9 (14) (2012)
Yaohua Wang, Kai Zhang, Jianghua Wan, Sheng Liu, Xi Ning, Shuming Chen
Architectural Implications for SIMD Processors in the Wireless Communication Domain. HPCC-ICESS (2012)
Sheng Liu, Shuming Chen, Hu Chen, Yang Guo
A novel parallel memory organization supporting multiple access types with matched memory modules. IEICE Electron. Express 9 (6) (2012)
Sheng Liu, Shuming Chen, Jianghua Wan, Haiyan Chen, Yaohua Wang
Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle. NAS (2011)
Kai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang
Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs. ASICON (2011)
Hu Chen, Sheng Liu, Shuming Chen
A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding. NAS (2011)
Sheng Liu, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang, Yaohua Wang
LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs. IEICE Electron. Express 8 (24) (2011)
Sheng Liu, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen
Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs. NAS (2011)
Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. HPCC (2010)