Junzhong Shen

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 27

Top Topics

Pipelined Architecture

Efficient Implementation

Convolutional Neural Networks

Top Venues

HPCC/DSS/SmartCity/DependSys

Publications

Bingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng, Wei Guo
MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core Processor. DATE (2024)
Jing Feng, Mei Wen, Xin Ju, Junzhong Shen, Yang Guo
Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency. ISCAS (2024)
Bingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng, Wei Guo
MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-core Processor. CoRR (2024)
Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. ICCD (2022)
Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang
S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness. ISCAS (2022)
Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. CoRR (2022)
Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys (2022)
Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation. ISPASS (2022)
Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP (2022)
Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li
Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators. HPCC/DSS/SmartCity/DependSys (2021)
Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang
SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. HPCC/DSS/SmartCity/DependSys (2021)
Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA (2020)
Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. DAC (2020)
Junzhong Shen, You Huang, Mei Wen, Chunyuan Zhang
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang
Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform. ICA3PP (1) (2020)
Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. IEEE Access 8 (2020)
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. ISCAS (2019)
Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. FPGA (2019)
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform. ICPP (2019)
Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System. DAC (2019)
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs. CoRR (2019)
Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. CoRR (2018)
You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA. IEICE Electron. Express 15 (10) (2018)
Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA. FPGA (2018)
Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs. ISCAS (2018)
Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC (2017)
Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29 (20) (2017)
Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) (2015)