Qianming Yang

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 9

Top Topics

Convolutional Neural Networks

Interval Arithmetic

Heterogeneous Platforms

Floating Point Unit

Top Venues

IEICE Trans. Inf. Syst.

Concurr. Comput. Pract. Exp.

Publications

Hongbing Tan, Libo Huang, Zhong Zheng, Hui Guo, Qianming Yang, Li Shen, Gang Chen, Liquan Xiao, Nong Xiao
A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Jing Zhang, Libo Huang, Hongbing Tan, Ling Yang, Zhong Zheng, Qianming Yang
Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning. ACM Great Lakes Symposium on VLSI (2023)
Hongbing Tan, Run Yan, Ling Yang, Libo Huang, Liquan Xiao, Qianming Yang
Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications. ICA3PP (2022)
Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. IEEE Access 8 (2020)
Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang
Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. INFOCOM Workshops (2019)
Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. NPC (2017)
Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. Concurr. Comput. Pract. Exp. 29 (20) (2017)
Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang
Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. IEICE Trans. Inf. Syst. (4) (2015)
Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. ICA3PP (1) (2015)
Yaping Liu, Zhihong Liu, Baosheng Wang, Qianming Yang
SIR: A Secure Identifier-Based Inter-Domain Routing for Identifier/Locator Split Network. IEICE Trans. Commun. (7) (2013)
Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai, Chunyuan Zhang, Qianming Yang
Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. IEICE Trans. Inf. Syst. (12) (2013)
Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. J. Supercomput. 63 (2) (2013)
Yi He, Maolin Guan, Chunyuan Zhang, Tian Tian, Qianming Yang
Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression. HPCC-ICESS (2012)
Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao
The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). FPGA (2012)
Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang
Tiled Multi-Core Stream Architecture. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. DSD (2010)
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang
SAT: A Stream Architecture Template for Embedded Applications. CIT (2010)
Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun
On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. IEEE Micro 28 (4) (2008)
Yi He, Ju Ren, Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang
FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture. ACSAC (2008)
Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun
FT64: Scientific Computing with Streams. HiPC (2007)
Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang
A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. Asia-Pacific Computer Systems Architecture Conference (2007)