Manish Kumar Jaiswal

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 12

Top Topics

Design Space Exploration

Fpga Implementation

Sparse Matrices

Top Venues

Circuits Syst. Signal Process.

IEEE Trans. Circuits Syst. I Regul. Pap.

IPDPS Workshops

Publications

Manish Kumar Jaiswal, Hayden Kwok-Hay So
PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access 7 (2019)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Design of quadruple precision multiplier architectures with SIMD single and double precision support. Integr. 65 (2019)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Universal number posit arithmetic generator on FPGA. DATE (2018)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS (2018)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. Circuits Syst. Signal Process. 37 (1) (2018)
Farkhanda Syed, Zahid Ullah, Manish Kumar Jaiswal
Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA. IEEE Embed. Syst. Lett. 10 (3) (2018)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision division architecture. MWSCAS (2016)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Taylor Series Based Architecture for Quadruple Precision Floating Point Division. ISVLSI (2016)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Architecture for quadruple precision floating point division with multi-precision support. ASAP (2016)
Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So
High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig (2016)
Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT (2016)
Manish Kumar Jaiswal, Hayden Kwok-Hay So
Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC (2015)
Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
Z-TCAM: An SRAM-based Architecture for TCAM. IEEE Trans. Very Large Scale Integr. Syst. 23 (2) (2015)
Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI (2015)
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI (2014)
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33 (11) (2014)
Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
E-TCAM: An Efficient SRAM-Based Architecture for TCAM. Circuits Syst. Signal Process. 33 (10) (2014)
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
Manish Kumar Jaiswal, Ray C. C. Cheung
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectron. J. 44 (5) (2013)
Manish Kumar Jaiswal, Ray C. C. Cheung
VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique. Circuits Syst. Signal Process. 32 (1) (2013)
Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). FPL (2013)
Manish Kumar Jaiswal, Ray C. C. Cheung
Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier. IPDPS Workshops (2012)
Manish Kumar Jaiswal, Ray C. C. Cheung
High Performance Reconfigurable Architecture for Double Precision Floating Point Division. ARC (2012)
Zahid Ullah, Manish Kumar Jaiswal, Y. C. Chan, Ray C. C. Cheung
FPGA Implementation of SRAM-based Ternary Content Addressable Memory. IPDPS Workshops (2012)
Manish Kumar Jaiswal, Nitin Chandrachoodan
FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. IEEE Trans. Computers 61 (1) (2012)
Manish Kumar Jaiswal, Ray C. C. Cheung
Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. FCCM (2012)
Manish Kumar Jaiswal, Nitin Chandrachoodan
Efficient Implementation of Floating-Point Reciprocator on FPGA. VLSI Design (2009)
Manish Kumar Jaiswal, Nitin Chandrachoodan
Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA. ICIIS (2008)