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Architecture for Dual-Mode Quadruple Precision Floating Point Adder.
Manish Kumar Jaiswal
B. Sharat Chandra Varma
Hayden Kwok-Hay So
Published in:
ISVLSI (2015)
Keyphrases
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floating point
instruction set
floating point arithmetic
square root
fixed point
data flow
sparse matrices
floating point unit
low cost
fourier transform
computer architecture