Architecture for Dual-Mode Quadruple Precision Floating Point Adder.

Manish Kumar Jaiswal B. Sharat Chandra Varma Hayden Kwok-Hay So

Published in: ISVLSI (2015)

Keyphrases

floating point
instruction set
floating point arithmetic
square root
fixed point
data flow
sparse matrices
floating point unit
low cost
fourier transform
computer architecture