Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support.
Manish Kumar JaiswalRay C. C. CheungPublished in: Microelectron. J. (2013)
Keyphrases
- hardware implementation
- high precision
- low cost
- cost effective
- end users
- field programmable gate array
- precision and recall
- floating point
- case study
- reconfigurable architecture
- parallel algorithm
- efficient implementation
- computationally efficient
- primal dual
- parallel architecture
- hardware architecture
- high recall
- dynamic reconfiguration
- digital signal