Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier.

Manish Kumar Jaiswal Ray C. C. Cheung

Published in: IPDPS Workshops (2012)

Keyphrases

floating point
sparse matrices
fpga implementation
square root
fixed point
instruction set
real time
general purpose
hardware implementation
interval arithmetic
floating point arithmetic
neural network
pattern recognition
dynamic programming
data processing
efficient implementation