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Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.
Manish Kumar Jaiswal
Ray C. C. Cheung
M. Balakrishnan
Kolin Paul
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2014)
Keyphrases
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floating point
floating point arithmetic
instruction set
fixed point
square root
data flow
graphics processing units
sparse matrices
level parallelism
processing units
application specific
database systems
database management systems
interval arithmetic
multi view
general purpose
floating point unit
search space