M. Balakrishnan

Publication Activity (10 Years)

Years Active: 1982-2022
Publications (10 Years): 28

Top Venues

VLSI Design

ISVLSI

Electron. Notes Discret. Math.

DSD

Publications

Vikas Upadhyay, Kashi Roy, M. Balakrishnan
Beacon Placement and Signal Strength Estimation to Improve Localization Coverage and Accuracy. IPIN (2022)
M. Balakrishnan
Computing and assistive technology solutions for the visually impaired. Commun. ACM 65 (11) (2022)
Shikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan
EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space Exploration. FPT (2022)
Solomon Abera, M. Balakrishnan, Anshul Kumar
Performance-Energy Trade-off in Modern CMPs. ACM Trans. Archit. Code Optim. 18 (1) (2021)
Anupam Sobti, Vaibhav Mavi, M. Balakrishnan, Chetan Arora
VmAP: A Fair Metric for Video Object Detection. ACM Multimedia (2021)
Vikas Upadhyay, M. Balakrishnan
Accessibility of Healthcare Facility for Persons with Visual Disability. PerCom Workshops (2021)
Rajesh Kedia, Shikha Goel, M. Balakrishnan, Kolin Paul, Rijurekha Sen
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators. IEEE Embed. Syst. Lett. 13 (3) (2021)
Shikha Goel, M. Balakrishnan, Rijurekha Sen
EnergyNN: Energy Estimation for Neural Network Inference Tasks on DPU. FPL (2021)
M. Balakrishnan
ASSISTECH: An Accidental Journey into Assistive Technology. A Journey of Embedded and Cyber-Physical Systems (2021)
Balasamy Krishnasamy, M. Balakrishnan, Arockia Christopher
A Genetic Algorithm Based Medical Image Watermarking for Improving Robustness and Fidelity in Wavelet Domain. FICTA (2) (2020)
Shikha Goel, Rajesh Kedia, M. Balakrishnan, Rijurekha Sen
INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs. FPT (2020)
Rajesh Kedia, M. Balakrishnan, Kolin Paul
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress. CODES+ISSS (2019)
Richa Gupta, P. V. M. Rao, M. Balakrishnan, S. Mannheimer
Evaluating the Use of Variable Height in Tactile Graphics. WHC (2019)
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority. J. Electron. Test. 35 (5) (2019)
Rajesh Kedia, M. Balakrishnan, Kolin Paul
GRanDE: Graphical Representation and Design Space Exploration of Embedded Systems. DSD (2019)
Solomon Abera Bekele, M. Balakrishnan, Anshul Kumar
ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling. SpringSim (2019)
Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora
MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources. VLSI Design (2019)
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. VLSI Design (2019)
Anupam Sobti, M. Balakrishnan, Chetan Arora
Multi-sensor Energy Efficient Obstacle Detection. DSD (2019)
Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan
Task Assignment Algorithms for Multicore Platforms with Process Variations. J. Low Power Electron. 14 (2) (2018)
Solomon Abera, M. Balakrishnan, Anshul Kumar
Performance-Energy Trade-off in CMPs with Per-Core DVFS. ARCS (2018)
Anupam Sobti, Chetan Arora, M. Balakrishnan
Object Detection in Real-Time Systems: Going Beyond Precision. WACV (2018)
Suman Adhepalli Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan, P. V. M. Rao
FPGA-Based Controllers for Compact Low Power Refreshable Braille Display. ISVLSI (2018)
Solomon Abera, M. Balakrishnan, Anshul Kumar
PLSS: A Scheduler for Multi-core Embedded Systems. ARCS (2017)
Mansureh Shahraki Moghaddam, M. Balakrishnan, Kiyoung Choi
Optimal mapping of program overlays onto many-core platforms with limited memory capacity. Des. Autom. Embed. Syst. 21 (3-4) (2017)
Rajesh Kedia, K. K. Yoosuf, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, M. Balakrishnan
MAVI: An Embedded Device to Assist Mobility of Visually Impaired. VLSI Design (2017)
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier
Hardware acceleration of de novo genome assembly. Int. J. Embed. Syst. 9 (1) (2017)
Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms. ISVLSI (2016)
Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung
Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Mansureh Shahraki Moghaddam, M. Balakrishnan, Kolin Paul
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform. ARC (2015)
M. Balakrishnan, G. Marimuthu, S. Arumugam
Vertex in-magic arc labelings of digraphs. Electron. Notes Discret. Math. 48 (2015)
Arun Parakh, M. Balakrishnan, Kolin Paul
Improving Map-Reduce for GPUs with cache. Int. J. High Perform. Syst. Archit. 5 (3) (2015)
S. Arumugam, M. Balakrishnan, G. Marimuthu
E-Super Vertex In-Magic Total Labelings of Digraphs. Electron. Notes Discret. Math. 48 (2015)
G. Marimuthu, S. Kavitha, M. Balakrishnan
Super Edge Magic Graceful Labeling of Generalized Petersen Graphs. Electron. Notes Discret. Math. 48 (2015)
Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array. FCCM (2014)
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI (2014)
Smruti R. Sarangi, Gayathri Ananthanarayanan, M. Balakrishnan
LightSim: A leakage aware ultrafast temperature simulator. ASP-DAC (2014)
G. Marimuthu, M. Balakrishnan
Super edge magic graceful graphs. Inf. Sci. 287 (2014)
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. 33 (11) (2014)
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs. DSD (2014)
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs. VLSI Design (2014)
Mrinal Mech, Kunal Kwatra, Supriya Das, Piyush Chanana, Rohan Paul, M. Balakrishnan
Edutactile - A Tool for Rapid Generation of Accurate Guideline-Compliant Tactile Graphics for Science and Mathematics. ICCHP (2) (2014)
Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs (7) (2014)
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan, Dominique Lavenier
FAssem: FPGA Based Acceleration of De Novo Genome Assembly. FCCM (2013)
Gayathri Ananthanarayanan, Geetika Malhotra, M. Balakrishnan, Smruti R. Sarangi
Amdahl's law in the era of process variation. Int. J. High Perform. Syst. Archit. 4 (4) (2013)
B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan
Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design (2013)
Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan
Design and Implementation of High Performance Architectures with Partially Reconfigurable CGRAs. IPDPS Workshops (2013)
Dhruv Jain, Akhil Jain, Rohan Paul, Akhila Komarika, M. Balakrishnan
A path-guided audio based indoor navigation system for persons with visual impairment. ASSETS (2013)
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (4) (2012)
M. Balakrishnan, Hong Huang, Rafael Asorey-Cacheda, Satyajayant Misra, Sandeep Pawar, Yousef Jaradat
Measures and Countermeasures for Null Frequency Jamming of On-Demand Routing Protocols in Wireless Ad Hoc Networks. IEEE Trans. Wirel. Commun. 11 (11) (2012)
M. Balakrishnan
Power Consumption in Multi-core Processors. IC3 (2012)
Arun Parakh, M. Balakrishnan, Kolin Paul
Performance Estimation of GPUs with Cache. IPDPS Workshops (2012)
G. Marimuthu, M. Balakrishnan
E-super vertex magic labelings of graphs. Discret. Appl. Math. 160 (12) (2012)
Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi
Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60 (4) (2011)
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
Architecture and tools for programmable QCA. FPT (2011)
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 7 (3) (2011)
Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan
Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC (2010)
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
A tiled programmable fabric using QCA. FPT (2010)
Rajeswari Devadoss, Kolin Paul, M. Balakrishnan
Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design (2010)
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. ISLPED (2009)
Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE (2009)
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
Cache aware compression for processor debug support. DATE (2009)
Sonali Chouhan, Ranjan Bose, M. Balakrishnan
A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009)
Sonali Chouhan, Ranjan Bose, M. Balakrishnan
Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes. IEEE Trans. Wirel. Commun. 8 (10) (2009)
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
Online cache state dumping for processor debug. DAC (2009)
Sonali Chouhan, M. Balakrishnan, Ranjan Bose
A framework for energy consumption based design space exploration for wireless sensor nodes. ISLPED (2008)
M. Balakrishnan, N. Ravisankar, K. Meena, R. Elanchezhian, S. K. Zamir Ahmed
Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands. IICAI (2007)
Anup Gangwar, M. Balakrishnan, Anshul Kumar
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12 (1) (2007)
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Int. J. Parallel Program. 35 (6) (2007)
Ashutosh Pal, M. Balakrishnan
A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. FPL (2007)
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar
Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping (2006)
Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan
New approach to architectural synthesis: incorporating QoS constraint. EMSOFT (2006)
Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
Sequential Equivalence Checking. VLSI Design (2006)
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan
ADOPT: An Approach to Activity Based Delay Optimization. VLSI Design (2005)
M. Balakrishnan, B. S. Panwar
A Specialized Graduate Program in VLSI Design Tools and Technology. MSE (2005)
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
Integrated On-Chip Storage Evaluation in ASIP Synthesis. VLSI Design (2005)
Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). FPGA (2005)
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE (2005)
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
An efficient technique for exploring register file size in ASIP design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (12) (2004)
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS (2004)
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design (2004)
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
Exploring Storage Organization in ASIP Synthesis. DSD (2003)
Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar
SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design (2003)
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
An efficient technique for exploring register file size in ASIP synthesis. CASES (2002)
M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS (2002)
M. Balakrishnan, Anshul Kumar, C. P. Joshi
A New Performance Evaluation Approach for System Level Design Space Exploration. ISSS (2002)
Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar
Exploring the Number of Register Windows in ASIP Synthesis. VLSI Design (2002)
Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel
Scratchpad memory: design alternative for cache on-chip memory in embedded systems. CODES (2002)
M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke
Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. ISSS (2002)
Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. VLSI Design (2002)
M. Balakrishnan
A Specialized Graduate Program in VLSI Design: A Success Story. MSE (2001)
Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan
Analysis of the influence of register file size on energyconsumption, code size, and execution time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (11) (2001)
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
ASIP Design Methodologies : Survey and Issues. VLSI Design (2001)
Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan
Exploring design space of parallel realizations: MPEG-2 decoder case study. CODES (2001)
Anupam Rastogi, M. Balakrishnan, Anshul Kumar
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. VLSI Design (2001)
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan
Evaluating register file size in ASIP design. CODES (2001)
M. Balakrishnan, Heman Khanna
Allocation of FIFO structures in RTL data paths. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Arvind Rajawat, M. Balakrishnan, Anshul Kumar
nterface Synthesis: Issues and Approaches. VLSI Design (2000)
T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik
Processor Evaluation in an Embedded Systems Design Environment. VLSI Design (2000)
Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan
Speeding up power estimation of embedded software. ISLPED (2000)

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Publication Activity (10 Years)

Top Topics

Top Venues

M. Balakrishnan