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Anup Gangwar
Publication Activity (10 Years)
Years Active: 2002-2021
Publications (10 Years): 4
Top Topics
Real World
Synthetic Data
Texture Synthesis
Wide Range
Top Venues
ISPASS
DAC
ICCAD
ISVLSI
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Publications
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Sri Harsha Gade
,
Anup Gangwar
,
Ambica Prasad
,
Nitin Kumar Agarwal
,
Ravishankar Sreedharan
An Automated Traffic Generation Framework for Performance Evaluation of Networks-on-Chip for Real World Use Cases.
ISPASS
(2021)
Anup Gangwar
,
Ravishankar Sreedharan
,
Ambica Prasad
,
Nitin Kumar Agarwal
,
Sri Harsha Gade
Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip.
DAC
(2021)
Anup Gangwar
,
Nitin Kumar Agarwal
,
Ravishankar Sreedharan
,
Ambica Prasad
,
Sri Harsha Gade
,
Zheng Xu
Automated Synthesis of Custom Networks-on-Chip for Real World Applications.
ICCAD
(2020)
Anup Gangwar
,
Zheng Xu
,
Nitin Kumar Agarwal
,
Ravishankar Sreedharan
,
Ambica Prasad
Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral Specification.
ISVLSI
(2019)
Anup Gangwar
,
M. Balakrishnan
,
Anshul Kumar
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.
ACM Trans. Design Autom. Electr. Syst.
12 (1) (2007)
Anup Gangwar
,
M. Balakrishnan
,
Preeti Ranjan Panda
,
Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
Int. J. Parallel Program.
35 (6) (2007)
Ankit Mathur
,
Mayank Agarwal
,
Soumyadeb Mitra
,
Anup Gangwar
,
M. Balakrishnan
,
Subhashis Banerjee
SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).
FPGA
(2005)
Anup Gangwar
,
M. Balakrishnan
,
Preeti Ranjan Panda
,
Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
DATE
(2005)
Amarjeet Singh
,
Amit Chhabra
,
Anup Gangwar
,
Basant Kumar Dwivedi
,
M. Balakrishnan
,
Anshul Kumar
SoC Synthesis with Automatic Hardware Software Interface Generation.
VLSI Design
(2003)
M. Balakrishnan
,
Anshul Kumar
,
Paolo Ienne
,
Anup Gangwar
,
Bhuvan Middha
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.
ISSS
(2002)