Preeti Ranjan Panda

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 38

Top Venues

ACM Trans. Embed. Comput. Syst.

DATE

IEEE Trans. Very Large Scale Integr. Syst.

VLSI Design

Publications

Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. ACM Trans. Design Autom. Electr. Syst. 29 (1) (2024)
Shailja Pandey, Sayam Sethi, Preeti Ranjan Panda
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Aritra Bagchi, Dinesh Joshi, Preeti Ranjan Panda
COBRRA: COntention-aware cache Bypass with Request-Response Arbitration. ACM Trans. Embed. Comput. Syst. 23 (1) (2024)
Divya Praneetha Ravipati, Victor M. van Santen, Sami Salamin, Hussam Amrouch, Preeti Ranjan Panda
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. IEEE Trans. Very Large Scale Integr. Syst. 31 (9) (2023)
Preeti Ranjan Panda
Editorial. IEEE Embed. Syst. Lett. 15 (4) (2023)
Preeti Ranjan Panda, Shailja Pandey
Education Abstract: Thermal Challenges and Mitigation in 3D DRAM. CODES+ISSS (2023)
Lokesh Siddhu, Aritra Bagchi, Rajesh Kedia, Isaar Ahmad, Shailja Pandey, Preeti Ranjan Panda
Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure. ACM Trans. Embed. Comput. Syst. 22 (6) (2023)
Garima Modi, Aritra Bagchi, Neetu Jindal, Ayan Mandal, Preeti Ranjan Panda
CABARRE: Request Response Arbitration for Shared Cache Management. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Jörg Henkel, Preeti Ranjan Panda, Hussam Amrouch
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. IEEE Trans. Very Large Scale Integr. Syst. 30 (3) (2022)
Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. ACM Trans. Archit. Code Optim. 19 (3) (2022)
Preeti Ranjan Panda
Editorial. IEEE Embed. Syst. Lett. 14 (1) (2022)
Shailja Pandey, Preeti Ranjan Panda
NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda
CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance. DATE (2022)
Lokesh Siddhu, Rajesh Kedia, Shailja Pandey, Martin Rapp, Anuj Pathania, Jörg Henkel, Preeti Ranjan Panda
CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. CoRR (2021)
Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda
Leakage-Aware Dynamic Thermal Management of 3D Memories. ACM Trans. Design Autom. Electr. Syst. 26 (2) (2021)
Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda
A Survey of Cache Simulators. ACM Comput. Surv. 53 (1) (2020)
Neetu Jindal, Shubhani Gupta, Divya Praneetha Ravipati, Preeti Ranjan Panda, Smruti R. Sarangi
Enhancing Network-on-Chip Performance by Reusing Trace Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Preeti Ranjan Panda
Editorial-December 2020. IEEE Embed. Syst. Lett. 12 (4) (2020)
Sakshi Tiwari, Shreshth Tuli, Isaar Ahmad, Ayushi Agarwal, Preeti Ranjan Panda, Sreenivas Subramoney
REAL: REquest Arbitration in Last Level Caches. ACM Trans. Embed. Comput. Syst. 18 (6) (2020)
Neetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli
DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring. DAC (2019)
Hadi Brais, Preeti Ranjan Panda
Alleria: An Advanced Memory Access Profiling Framework. ACM Trans. Embed. Comput. Syst. 18 (5s) (2019)
Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra
Techniques for Debug of Low Power SoCs. MTV (2019)
Lokesh Siddhu, Preeti Ranjan Panda
PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor. ACM Trans. Embed. Comput. Syst. 18 (5s) (2019)
Vivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri
Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. VLSI Design (2019)
Lokesh Siddhu, Preeti Ranjan Panda
FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories. DATE (2019)
Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi
Reusing Trace Buffers as Victim Caches. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Preeti Ranjan Panda, Namita Sharma, Srikanth Kurra, Khushboo Anil Bhartia, Neeraj Kumar Singh
Exploration of Loop Unroll Factors in High Level Synthesis. VLSI Design (2018)
Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi
Reusing trace buffers to enhance cache performance. DATE (2017)
Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. DATE (2017)
Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network. ACM Trans. Archit. Code Optim. 14 (4) (2017)
Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi, Ayan Bhattacharyya, Deepak Chauhan, Sharad Kumar
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 25 (6) (2017)
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Min Li, Prashant Agrawal
Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD. ACM Trans. Embed. Comput. Syst. 15 (1) (2016)
Sandeep Chandran, Preeti Ranjan Panda, Deepak Chauhan, Sharad Kumar, Smruti R. Sarangi
Extending trace history through tapered summaries in post-silicon validation. ASP-DAC (2016)
Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda
Area-Aware Cache Update Trackers for Postsilicon Validation. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. DATE (2016)
Iason Filippopoulos, Namita Sharma, Francky Catthoor, Per Gunnar Kjeldsberg, Preeti Ranjan Panda
Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures. ACM Trans. Embed. Comput. Syst. 15 (3) (2016)
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi
A Generic Implementation of Barriers Using Optical Interconnects. VLSI Design (2016)
Prasenjit Chakraborty, Preeti Ranjan Panda, Sandeep Sen
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures. ACM Trans. Design Autom. Electr. Syst. 22 (1) (2016)
Preeti Ranjan Panda, Vishal Patel, Praxal Shah, Namita Sharma, Vaidyanathan Srinivasan, Dipankar Sarma
Power Optimization Techniques for DDR3 SDRAM. VLSI Design (2015)
Sandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi
Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects. CoRR (2015)
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa
Array Interleaving - An Energy-Efficient Data Layout Transformation. ACM Trans. Design Autom. Electr. Syst. 20 (3) (2015)
Namita Sharma, Preeti Ranjan Panda, Francky Catthoor
Energy efficient FFT implementation through stage skipping and merging. CODES+ISSS (2015)
Preeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan
Array scalarization in high level synthesis. ASP-DAC (2014)
Namita Sharma, Preeti Ranjan Panda, Min Li, Prashant Agrawal, Francky Catthoor
Energy efficient data flow transformation for Givens Rotation based QR Decomposition. DATE (2014)
Preeti Ranjan Panda, Sourav Roy, Srikanth Chandrasekaran, Namita Sharma, Jasleen Kaur, Sarath Kumar Kandalam, Nagaraj N.
High level energy modeling of controller logic in data caches. ACM Great Lakes Symposium on VLSI (2014)
Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan
Energy optimization in Android applications through wakelock placement. DATE (2014)
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
Shared-port register file architecture for low-energy VLIW processors. ACM Trans. Archit. Code Optim. 11 (1) (2014)
Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda
Space sensitive cache dumping for post-silicon validation. DATE (2013)
Preeti Ranjan Panda, Manoj Jain, Anubha Verma, Dipankar Sarma, Vaidyanathan Srinivasan
Power Supply Efficiency Aware Server Allocation in Data Centers. VLSI Design (2013)
Namita Sharma, Tom Vander Aa, Prashant Agrawal, Praveen Raghavan, Preeti Ranjan Panda, Francky Catthoor
Data memory optimization in LTE downlink. ICASSP (2013)
Radu Marculescu, Preeti Ranjan Panda
Message from the program co-chairs. CODES+ISSS (2013)
Prasenjit Chakraborty, Preeti Ranjan Panda
SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems. CASES (2013)
Amit Kumar, Preeti Ranjan Panda, Smruti R. Sarangi
Efficient on-line algorithm for maintaining k-cover of sparse bit-strings. FSTTCS (2012)
Prasenjit Chakraborty, Preeti Ranjan Panda
Integrating software caches with scratch pad memory. CASES (2012)
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
Exploiting UML based validation for compliance checking of TLM 2 based models. Des. Autom. Embed. Syst. 16 (2) (2012)
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
A UML based framework for efficient validation of TLM 2 models. FDL (2011)
Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda
A SysML Profile for Development and Early Validation of TLM 2.0 Models. ECMFA (2011)
Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi
Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60 (4) (2011)
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
Exploiting temporal decoupling to accelerate trace-driven NoC emulation. CODES+ISSS (2011)
B. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda
Rank based dynamic voltage and frequency scaling fortiled graphics processors. CODES+ISSS (2010)
Preeti Ranjan Panda, Rajendran Panda
Guest Editorial: Special Issue on VLSI Design and Embedded Systems. Int. J. Parallel Program. 38 (3-4) (2010)
Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan
Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC (2010)
Anshul Kumar, Preeti Ranjan Panda
Front-End Design Flows for Systems on Chip: An Embedded Tutorial. VLSI Design (2010)
Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. CODES+ISSS (2010)
Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda
A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE (2009)
B. V. N. Silpa, Kumar S. S. Vemuri, Preeti Ranjan Panda
Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. ISVC (1) (2009)
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
Cache aware compression for processor debug support. DATE (2009)
Rajendran Panda, Preeti Ranjan Panda
"22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. J. Low Power Electron. 5 (3) (2009)
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
Online cache state dumping for processor debug. DAC (2009)
Preeti Ranjan Panda
Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems. Int. J. Parallel Program. 36 (1) (2008)
B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ICCAD (2008)
Pushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda
REWIRED - Register Write Inhibition by Resource Dedication. ASP-DAC (2008)
Rahul Jain, Preeti Ranjan Panda
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. VLSI Design (2007)
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
Customization of Register File Banking Architecture for Low Power. VLSI Design (2007)
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. VLSI Design (2007)
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Int. J. Parallel Program. 35 (6) (2007)
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan Panda
The impact of loop unrolling on controller delay in high level synthesis. DATE (2007)
Rahul Jain, Preeti Ranjan Panda
An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. ISCAS (2007)
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
Rapid estimation of control delay from high-level specifications. DAC (2006)
Preeti Ranjan Panda
Abridged addressing: a low power memory addressing strategy. ASP-DAC (2006)
Vikram Singh Saun, Preeti Ranjan Panda
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. VLSI Design (2005)
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE (2005)
Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
Specification and Design of Multi-Million Gate SOCs. VLSI Design (2003)
Preeti Ranjan Panda, Nikil D. Dutt
Memory Architectures for Embedded Systems-On-Chip. HiPC (2002)
Jaewon Seo, Taewhan Kim, Preeti Ranjan Panda
An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC (2002)
Preeti Ranjan Panda, Lakshmikantam Chitturi
An energy-conscious algorithm for memory port allocation. ICCAD (2002)
Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda
Embedded Memories in System Design: Technology, Application, Design and Tools. VLSI Design (2001)
Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg
Data and memory optimization techniques for embedded systems. ACM Trans. Design Autom. Electr. Syst. 6 (2) (2001)
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef
Data Memory Organization and Optimizations in Application-Specific Systems. IEEE Des. Test Comput. 18 (3) (2001)
Wolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda
New Design Paradigms: What Needs to be Standardized?. ISSS (2001)
Preeti Ranjan Panda
SystemC: A Modeling Platform Supporting Multiple Design Abstractions. ISSS (2001)
Preeti Ranjan Panda, Luc Séméria, Giovanni De Micheli
Cache-efficient memory layout of aggregate data structures. ISSS (2001)
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Preeti Ranjan Panda
Memory bank customization and assignment in behavioral synthesis. ICCAD (1999)
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
Local memory exploration and optimization in embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (1) (1999)
Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. IEEE Trans. Computers 48 (2) (1999)
Preeti Ranjan Panda, Nikil D. Dutt
Low-power memory mapping through reducing address bus activity. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
Incorporating DRAM access modes into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (2) (1998)
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
Data Cache Sizing for Embedded Processor Applications. DATE (1998)

Preeti Ranjan Panda.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Preeti Ranjan Panda