Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine.

B. V. N. Silpa Kumar S. S. Vemuri Preeti Ranjan Panda

Published in: ISVC (1) (2009)

Keyphrases

low power
low power consumption
power consumption
low cost
high speed
signal processor
high power
single chip
vlsi circuits
digital signal processing
wireless transmission
logic circuits
vertex set
gate array
cmos technology
vlsi architecture
power saving
image sensor
low complexity