G. S. Visweswaran

Publication Activity (10 Years)

Years Active: 1997-2018
Publications (10 Years): 11

Top Topics

Cmos Technology

Rademacher Complexity

Error Detection And Correction

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ashish Kumar, G. S. Visweswaran
A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias. VLSI Design (2018)
Roohie Kaushik, Shouri Chatterjee, G. S. Visweswaran
Charge-Controlled Oscillators and Their Application in Frequency Synthesis. IEEE Trans. Circuits Syst. II Express Briefs (10) (2017)
Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Nidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. VDAT (2016)
Ashish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. VLSI Design (2016)
Nidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad S. Hashmi, G. S. Visweswaran, Anuj Grover
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation. SoCC (2016)
Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. SoCC (2016)
Surya Piplani, G. S. Visweswaran, Anshul Kumar
Impact of crosstalk and process variation on capture power reduction for at-speed test. VTS (2016)
Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha
A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation. ICICDT (2015)
Anuj Grover, Promod Kumar, Mohammad Daud, G. S. Visweswaran, Chittoor R. Parthasarathy, Jean-Philippe Noel, David Turgis, Bastien Giraud, Guillaume Moritz
Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. ICICDT (2015)
Ashish Kumar, G. S. Visweswaran, Kaushik Saha
Low voltage error resilient SRAM using run-time error detection and correction. ESSCIRC (2015)
G. S. Visweswaran, Pragya Varshney, Maneesha Gupta
New Approach to Realize Fractional Power in z-Domain at Low Frequency. IEEE Trans. Circuits Syst. II Express Briefs (3) (2011)
Maneesha Gupta, Pragya Varshney, G. S. Visweswaran
Digital fractional-order differentiator and integrator models based on first-order and higher order operators. Int. J. Circuit Theory Appl. 39 (5) (2011)
Lalit K. Jiwani, Shiv Dutt Joshi, G. S. Visweswaran
FFT based sign modulated DWT filter bank. EUSIPCO (2010)
B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran
Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. ICCAD (2008)
Maneesha Gupta, Pragya Varshney, G. S. Visweswaran, B. Kumar
Novel Digital Differentiator and Corresponding Fractional Order Differentiator Models. SIGMAP (2008)
Venkat Rao, Nicolas Navet, Gaurav Singhal, Anshul Kumar, G. S. Visweswaran
Battery aware dynamic scheduling for periodic task graphs. IPDPS (2006)
Mukul Milind Ojha, Arun Kumar Anand, G. S. Visweswaran, D. Nagchoudhuri
A Relative Comparative Based Datapath for Increasing Resolution in a Capacitive Fingerprint Sensor Chip. VLSI Design (2005)
Tushar S. Shelar, G. S. Visweswaran
Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. VLSI Design (2004)
Sanjeev Kumar Maheshwari, G. S. Visweswaran
A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer. VLSI Design (2000)
Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran
Jitter Estimation Methodology for Clock Chips. VLSI Design (2000)
Basabi Bhaumik, G. S. Visweswaran, R. Lakshminarasimhan
A New Test Compression Scheme. VLSI Design (1999)
Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi
A Low Power 256 KB SRAM Design. VLSI Design (1999)
Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri
Current Mode Ternary D/A Converter. VLSI Design (1998)
Saeid Nooshabadi, Juan A. Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhuri
Micropipeline Architecture for Multiplier-less FIR Filters. VLSI Design (1997)