A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.
Anuj GroverG. S. VisweswaranChittoor R. ParthasarathyMohammad DaudDavid TurgisBastien GiraudJean-Philippe NoelIvan Miro PanadesGuillaume MoritzEdith BeignéPhilippe FlatressePromod KumarShamsi AzmiPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2017)
Keyphrases
- data dependent
- power consumption
- nm technology
- clock gating
- random access memory
- cmos technology
- low power
- low voltage
- high speed
- power reduction
- clock frequency
- power dissipation
- design considerations
- embedded dram
- risk bounds
- rademacher complexity
- parallel processing
- energy functional
- hash functions
- dynamic random access memory