A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias.

Ashish Kumar G. S. Visweswaran

Published in: VLSI Design (2018)

Keyphrases

cmos technology
high density
low power
power consumption
high speed
low voltage
leakage current
low density
spl times
data center
parallel processing
low cost
power dissipation
embedded dram
image sensor
silicon on insulator
thin film
field effect transistors
random access memory
magnetic tape