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Enhancing Network-on-Chip Performance by Reusing Trace Buffers.
Neetu Jindal
Shubhani Gupta
Divya Praneetha Ravipati
Preeti Ranjan Panda
Smruti R. Sarangi
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
Keyphrases
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network on chip
routing algorithm
network simulator
multi processor
data transfer
packet switched
real time
anomaly detection
multistage
parallel algorithm
data access