Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA.
Manish Kumar JaiswalNitin ChandrachoodanPublished in: ICIIS (2008)
Keyphrases
- efficient implementation
- floating point
- floating point arithmetic
- hardware implementation
- square root
- fixed point
- field programmable gate array
- active set
- floating point unit
- efficient processing
- sparse matrices
- instruction set
- fast fourier transform
- hardware architecture
- highly parallel
- interval arithmetic
- reinforcement learning