Oliver Diessel

Publication Activity (10 Years)

Years Active: 1996-2022
Publications (10 Years): 22

Top Topics

Code Generation

Video Processing

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Tong Wu, Oliver Diessel
Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work. FCCM (2022)
Junning Fan, Oliver Diessel
On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs. FCCM (2022)
Fernanda Lima, Oliver Diessel
Introduction to RAW 2019. IPDPS Workshops (2019)
Alexander Kroh, Oliver Diessel
Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform. ACM Trans. Reconfigurable Technol. Syst. 11 (4) (2019)
Nguyen Tran Huu Nguyen, Ediz Cetin, Oliver Diessel
Scheduling configuration memory error checks to improve the reliability of FPGA-based systems. IET Comput. Digit. Tech. 13 (3) (2019)
Dimitris Agiakatsikas, Ediz Cetin, Oliver Diessel
FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs. IEEE Trans. Aerosp. Electron. Syst. 54 (6) (2018)
Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel
From C to Fault-Tolerant FPGA-Based Systems. FCCM (2018)
Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong
Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery. Microprocess. Microsystems 60 (2018)
Alexander Kroh, Oliver Diessel
A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms. FPT (2018)
Zhuoran Zhao, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ganghee Lee, Ediz Cetin, Oliver Diessel
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
Ganghee Lee, Ediz Cetin, Oliver Diessel
Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel
Scheduling Considerations for Voter Checking in TMR-MER Systems. FCCM (2017)
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10 (2) (2017)
Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. FCCM (2017)
Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel
Reliable SEU monitoring and recovery using a programmable configuration controller. FPL (2017)
Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel
Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. DFT (2017)
Chao Wang, Xi Li, Yunji Chen, Youhui Zhang, Oliver Diessel, Xuehai Zhou
Service-Oriented Architecture on FPGA-Based MPSoC. IEEE Trans. Parallel Distributed Syst. 28 (10) (2017)
Lingkan Gong, Tong Wu, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Ediz Cetin, Oliver Diessel
A Programmable Configuration Controller for fault-tolerant applications. FPT (2016)
Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs. FPL (2016)
Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel
Dynamic scheduling of voter checks in FPGA-based TMR systems. FPT (2016)
Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong
Reconfiguration Control Networks for TMR Systems with Module-Based Recovery. FCCM (2016)
Zhuoran Zhao, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Çetin, Oliver Diessel
Fine-grained module-based error recovery in FPGA-based TMR systems. FPT (2016)
Ediz Cetin, Oliver Diessel, Lingkan Gong
Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets. ISCAS (2015)
Vinh T. Tran, Nagaraj Channarayapatna Shivaramaiah, Oliver Diessel, Andrew G. Dempster
A programmable multi-GNSS baseband receiver. ISCAS (2015)
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
Significant papers from the first 25 years of the FPL conference. FPL (2015)
Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai
Reconfiguration network design for SEU recovery in FPGAs. ISCAS (2014)
Lingkan Gong, Oliver Diessel
Simulation-based functional verification of dynamically reconfigurable systems. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai
Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. FPL (2013)
Lingkan Gong, Oliver Diessel, Johny Paul, Walter Stechele
RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. IPDPS Workshops (2013)
Lingkan Gong, Oliver Diessel
Functionally verifying state saving and restoration in dynamically reconfigurable systems. FPGA (2012)
Lesley Shannon, Oliver Diessel, Neil W. Bergmann
Guest Editorial: Field-Programmable Technology. J. Signal Process. Syst. 67 (1) (2012)
Lingkan Gong, Oliver Diessel
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification. FCCM (2011)
Lingkan Gong, Oliver Diessel
ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration. FPT (2011)
Shannon Koh, Oliver Diessel
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 3 (1) (2010)
Benjamin Kwek, Freddie Sunarso, Melissa Teoh, Arrian van Zal, Philip Preston, Oliver Diessel
FPGA-based video processing for a vision prosthesis. FPT (2010)
Branislav Hredzak, Oliver Diessel
Towards Dilated Placement of Dynamic NoC Cores. Dynamically Reconfigurable Architectures (2010)
Shannon Koh, Oliver Diessel
The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. FCCM (2008)
Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik
ACS: An Addressless Configuration Support for efficient partial reconfigurations. FPT (2008)
Shannon Koh, Oliver Diessel
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. FPL (2007)
Shannon Koh, Oliver Diessel
COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs. FCCM (2006)
Oliver Diessel, Shannon Koh
Enabling RTR for industry. Dynamically Reconfigurable Architectures (2006)
Usama Malik, Oliver Diessel
The Entropy of FPGA Reconfiguration. FPL (2006)
Lih Wen Koh, Oliver Diessel
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. Asia-Pacific Computer Systems Architecture Conference (2006)
Shannon Koh, Oliver Diessel
Communications infrastructure generation for modular FPGA reconfiguration. FPT (2006)
Shannon Koh, Oliver Diessel
COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. ARCS Workshops (2006)
Marco Torre, Usama Malik, Oliver Diessel
A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs. Asia-Pacific Computer Systems Architecture Conference (2005)
Usama Malik, Oliver Diessel
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs. FPL (2005)
Bernd Scheuermann, Keith So, Michael Guntsch, Martin Middendorf, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck
FPGA implementation of population-based ant colony optimization. Appl. Soft Comput. 4 (3) (2004)
Usama Malik, Oliver Diessel
On the placement and granularity of FPGA configurations. FPT (2004)
Oliver Diessel, Usama Malik, Keith So
Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs (Research Note). Euro-Par (2002)
Usama Malik, Keith So, Oliver Diessel
Resource-aware run-time elaboration of behavioural FPGA specifications. FPT (2002)
Michael Guntsch, Martin Middendorf, Bernd Scheuermann, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck, Keith So
Population based ant colony optimization on FPGA. FPT (2002)
Oliver Diessel, Usama Malik
An FPGA Interpreter with Virtual Hardware Management. IPDPS (2002)
Gordon J. Brebner, Oliver Diessel
Chip-Based Reconfigurable Task Management. FPL (2001)
Oliver Diessel, Hossam A. ElGindy
On Dynamic Task Scheduling for EPGA-Based Systems. Int. J. Found. Comput. Sci. 12 (5) (2001)
Oliver Diessel, George J. Milne
Behavioural Language Compilation with Virtual Hardware Management. FPL (2000)
Oliver Diessel, George J. Milne
Compiling Process Algebraic Descriptions into Reconfigurable Logic. IPDPS Workshops (2000)
Hossam A. ElGindy, Viktor K. Prasanna, Hartmut Schmeck, Oliver Diessel
Configurable Architectures Workshop (RAW 2000). IPDPS Workshops (2000)
Oliver Diessel, David A. Kearney, Grant B. Wigley
A Web-Based Multiuser Operating System for Reconfiguarble Computing. IPPS/SPDP Workshops (1999)
Oliver Diessel, Hossam A. ElGindy
Partial FPGA Rearrangement by Local Repacking (Abstract). FPGA (1998)
Oliver Diessel, Hossam A. ElGindy
Partial Rearrangements of Space-Shared FPGAs. IPPS/SPDP Workshops (1998)
Oliver Diessel, Hossam A. ElGindy
Run-time compaction of FPGA designs. FPL (1997)
Bryan Beresford-Smith, Oliver Diessel, Hossam A. ElGindy
Optimal Algorithms for Constrained Reconfigurable Meshes. J. Parallel Distributed Comput. 39 (1) (1996)