Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets.
Ediz CetinOliver DiesselLingkan GongPublished in: ISCAS (2015)
Keyphrases
- field programmable gate array
- high speed
- hardware implementation
- memory requirements
- power reduction
- digital signal processors
- memory usage
- memory size
- hardware architecture
- parallel hardware
- random access memory
- delay insensitive
- power dissipation
- processing elements
- real time
- computing power
- computational power
- image processing
- low power consumption
- embedded systems