Gordon J. Brebner

Publication Activity (10 Years)

Years Active: 1981-2022
Publications (10 Years): 9

Top Topics

Hardware And Software

Abstraction Layer

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. ICDCS (2022)
Haris Javaid, Ji Yang, Nathania Santoso, Mohit Upadhyay, Sundararajarao Mohan, Chengchen Hu, Gordon J. Brebner
Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric. CoRR (2021)
Siyi Qiao, Chengchen Hu, Gordon J. Brebner, Jianhua Zou, Xiaohong Guan
Adaptable Switch: A Heterogeneous Switch Architecture for Network-Centric Computing. IEEE Commun. Mag. 58 (12) (2020)
Guanwen Zhong, Haris Javaid, Hassaan Saadat, Lingchao Xu, Chengchen Hu, Gordon J. Brebner
FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy. CVCBT (2019)
Stephen Ibanez, Gianni Antichi, Gordon J. Brebner, Nick McKeown
Event-Driven Packet Processing. HotNets (2019)
Haris Javaid, Chengchen Hu, Gordon J. Brebner
Optimizing Validation Phase of Hyperledger Fabric. MASCOTS (2019)
Stephen Ibanez, Gordon J. Brebner, Nick McKeown, Noa Zilberman
The P4->NetFPGA Workflow for Line-Rate Packet Processing. FPGA (2019)
Haris Javaid, Chengchen Hu, Gordon J. Brebner
Optimizing Validation Phase of Hyperledger Fabric. CoRR (2019)
Huynh Tu Dang, Han Wang, Theo Jepsen, Gordon J. Brebner, Changhoon Kim, Jennifer Rexford, Robert Soulé, Hakim Weatherspoon
Whippersnapper: A P4 Language Benchmark Suite. SOSR (2017)
Gordon J. Brebner
Programmable hardware in software defined networking. OFC (2015)
Gordon J. Brebner
Programmable hardware for high performance SDN. OFC (2015)
Gordon J. Brebner
Programmable hardware for software defined networks. ECOC (2015)
Gordon J. Brebner, Weirong Jiang
High-Speed Packet Processing using Reconfigurable Computing. IEEE Micro 34 (1) (2014)
Christopher E. Neely, Gordon J. Brebner, Weijia Shang
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 6 (1) (2013)
Gordon J. Brebner
Softly defined networking. ANCS (2012)
Thilan Ganegedara, Viktor K. Prasanna, Gordon J. Brebner
Optimizing packet lookup in time and space on FPGA. FPL (2012)
Michael Attig, Gordon J. Brebner
400 Gb/s Programmable Packet Parsing on a Single FPGA. ANCS (2011)
Gordon J. Brebner
Reconfigurable Computing for High Performance Networking Applications. ARC (2011)
Christopher E. Neely, Gordon J. Brebner, Weijia Shang
Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration. FPL (2010)
Christopher E. Neely, Gordon J. Brebner, Weijia Shang
ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs. FCCM (2010)
Gordon J. Brebner
Packets everywhere: The great opportunity for field programmable technology. FPT (2009)
Shuvra S. Bhattacharyya, Gordon J. Brebner, Jörn W. Janneck, Johan Eker, Carl von Platen, Marco Mattavelli, Mickaël Raulet
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems. SIGARCH Comput. Archit. News 36 (5) (2008)
Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong
Editorial for the Special Issue on Field Programmable Technology. J. VLSI Signal Process. 47 (1) (2007)
Chidamber Kulkarni, Gordon J. Brebner
Memory centric thread synchronization on platform FPGAs. DATE (2006)
Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures (2006)
Jike Chong, Chidamber Kulkarni, Gordon J. Brebner
Building a flexible and scalable DRAM interface for networking applications on FPGAs. FPGA (2006)
Michael Attig, Gordon J. Brebner
Systematic Characterization of Programmable Packet Processing Pipelines. FCCM (2006)
Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures (2006)
Chidamber Kulkarni, Gordon J. Brebner
Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor. FPL (2006)
Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
Mutable Codesign for Embedded Protocol Processing. FCCM (2005)
Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
Mutable Codesign for Embedded Protocol Processing. FPL (2005)
Philip James-Roxby, Gordon J. Brebner
Multithreading in a Hyper-programmable Platform for Networked Systems. FPL (2004)
Gordon J. Brebner, Philip James-Roxby, Eric Keller, Chidamber Kulkarni
Hyper-Programmable Architectures for Adaptable Networked Systems. ASAP (2004)
Eric Keller, Gordon J. Brebner
Programming a hyper-programmable architecture for networked systems. FPT (2004)
Philip James-Roxby, Gordon J. Brebner, Dennis Bemmann
Time-Critical Software Deceleration in an FCCM. FCCM (2004)
Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle
Mapping a domain specific language to a platform FPGA. DAC (2004)
Gordon J. Brebner
Programmable Logic Has More Computational Power than Fixed Logic. FPL (2004)
Eric Keller, Gordon J. Brebner, Philip James-Roxby
Software Decelerators. FPL (2003)
Gordon J. Brebner
Eccentric SoC Architectures as the Future Norm. DSD (2003)
Gordon J. Brebner, Delon Levi
Networking on chip with platform FPGAs. FPT (2003)
Gordon J. Brebner
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. FCCM (2002)
Gordon J. Brebner
Multithreading for Logic-Centric Systems. FPL (2002)
Gordon J. Brebner
Workshop Introduction. IPDPS (2002)
Gordon J. Brebner, Irwin Kennedy
Circlets: Circuitry over the Internet. FCCM (2001)
Gordon J. Brebner, Oliver Diessel
Chip-Based Reconfigurable Task Management. FPL (2001)
Tim Kempster, Gordon J. Brebner, Peter Thanisch
A Transactional Approach to Configuring Telecommunications Services. Databases in Telecommunications (1999)
Gordon J. Brebner, Neil W. Bergmann
Reconfigurable Computing in Remote and Harsh Environments. FPL (1999)
Gordon J. Brebner
Circlets: Circuits as Applets. FCCM (1998)
Gordon J. Brebner
An Interactive Datasheet for the Xilinx XC6200. FPL (1998)
Gordon J. Brebner, Rob Pooley
ECOLE: A Configurable Environment for a Local Optical Network of Workstations. CANPC (1998)
Gordon J. Brebner
Field-Programmable Logic: Catalyst for New Computing Paradigms. FPL (1998)
Gordon J. Brebner, Adam Donlin
Runtime Reconfigurable Routing. IPPS/SPDP Workshops (1998)
Gordon J. Brebner
Automatc identification of swappable logic units in XC6200 circuitry. FPL (1997)
Gordon J. Brebner
The swappable logic unit: a paradigm for virtual hardware. FCCM (1997)
Gordon J. Brebner
A Virtual Hardware Operating System for the Xilinx XC6200. FPL (1996)
Gordon J. Brebner, John Gray
Use of Reconfigurability in Variable-Length Code Detection at Video Rates. FPL (1995)
Gordon J. Brebner
Configurable array logic circuits for computing network error detection codes. J. VLSI Signal Process. 6 (2) (1993)
Gordon J. Brebner
A CCS-based Investigation of Deadlock in a Multi-process Electronic Mail System. Formal Aspects Comput. 5 (5) (1993)
Leslie G. Valiant, Gordon J. Brebner
Universal Schemes for Parallel Communication STOC (1981)