Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices.
Shannon KohOliver DiesselPublished in: FPL (2007)
Keyphrases
- verilog hdl
- mobile devices
- random walk
- response time
- graph representation
- directed graph
- high speed
- bipartite graph
- graph theoretic
- graph model
- directed acyclic graph
- hardware implementation
- graph theory
- real time
- graph matching
- low cost
- mobile applications
- weighted graph
- context aware
- signal processing
- graph mining
- semi supervised
- image segmentation
- graph construction
- single chip
- real time image processing
- graph based algorithm
- neural network