A Soft Processor Overlay with Tightly-coupled FPGA Accelerator.
Ho-Cheung NgCheng LiuHayden Kwok-Hay SoPublished in: CoRR (2016)
Keyphrases
- tightly coupled
- field programmable gate array
- xilinx virtex
- fpga device
- single chip
- high speed
- general purpose processors
- general purpose
- hardware implementation
- digital signal
- fine grained
- gate array
- parallel architecture
- embedded systems
- parallel architectures
- high end
- systolic array
- loosely coupled
- parallel implementation
- parallel computing
- computing systems
- hardware architecture
- parallel processing
- hardware design
- image processing algorithms
- low power
- low cost
- clock frequency
- fpga implementation
- processing elements
- real time image processing
- instruction set
- high level
- real time
- computer architecture
- image processing
- web services
- massively parallel
- efficient implementation
- shared memory
- overlay network