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A technology mapper for depth-constrained FPGA logic cells.
Zhenghong Jiang
Grace Zgheib
Colin Yu Lin
David Novo
Zhihong Huang
Liqun Yang
Haigang Yang
Paolo Ienne
Published in:
FPL (2015)
Keyphrases
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high speed
data processing
case study
logic programming
cost effective
modal logic
rapid development
multi valued
real time image processing
gate array
neural network
three dimensional
image analysis
low cost
predicate logic
microscope images