Timing-constrained minimum area/power FPGA memory mapping.

Fangqing Du Colin Yu Lin Xiuhai Cui Jiabin Sun Feng Liu Fei Liu Haigang Yang

Published in: FPL (2013)

Keyphrases

computational power
power reduction
hardware implementation
parallel hardware
real time
power consumption

memory usage
memory space
computing power
memory requirements
high speed
multithreading

data structure
limited memory
single chip
real time image processing
data sets
low power

signal processing
field programmable gate array
power distribution
database systems
digital signal