Iyad Ouaiss

Publication Activity (10 Years)

Years Active: 1998-2020
Publications (10 Years): 1

Top Topics

Rapid Development

Hardware Implementation

Technological Advances

Engineering Problems

Top Venues

IEEE Trans. Educ.

J. Circuits Syst. Comput.

Publications

Mohammad Al-Abbas, Wissam Fawaz, Raymond Ghajar, Chadi Abou-Rjeily, Iyad Ouaiss, Zahi Nakad, George E. Nasr, Samer S. Saab
Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism Course. IEEE Trans. Educ. 63 (4) (2020)
Grace Zgheib, Iyad Ouaiss
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations. J. Circuits Syst. Comput. 24 (3) (2015)
Maria Abi Saad, Iyad Ouaiss
Priority-Driven Area Optimization in High-Level Synthesis. J. Circuits Syst. Comput. 20 (6) (2011)
Elie Elaaraj, Iyad Ouaiss
A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis. J. Circuits Syst. Comput. 20 (5) (2011)
Wissam Fawaz, Iyad Ouaiss, Ken Chen, Harry G. Perros
Deadline-based connection setup in wavelength-routed WDM networks. Comput. Networks 54 (11) (2010)
Samer S. Saab, Jad G. Hobeika, Iyad Ouaiss
A novel pseudorandom noise and band jammer generator using a composite sinusoidal function. IEEE Trans. Signal Process. 58 (2) (2010)
Annie Avakian, Iyad Ouaiss
Optimizing register binding in FPGAs using simulated annealing. ReConFig (2005)
Dalia Dagher, Iyad Ouaiss
Storage Allocation for Diverse FPGA Memory Specifications. FPL (2004)
Hassan Al Atat, Iyad Ouaiss
Register Binding for FPGAs with Embedded Memory. FCCM (2004)
Iyad Ouaiss, Ranga Vemuri
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. DATE (2001)
Amit Kasat, Iyad Ouaiss, Ranga Vemuri
Memory Synthesis for FPGA-Based Reconfigurable Computers. FPL (2001)
Iyad Ouaiss, Ranga Vemuri
Global memory mapping for FPGA-based reconfigurable systems. IPDPS (2001)
Iyad Ouaiss, Ranga Vemuri
Efficient Resource Arbitration in Reconfigurable Computing Environments. DATE (2000)
Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. DAC (1999)
Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops (1998)
Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
An Effective Design System for Dynamically Reconfigurable Architectures. FCCM (1998)