Meenakshi Kaul

Publication Activity (10 Years)

Years Active: 1998-2002
Publications (10 Years): 0

Publications

Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications. ACM Trans. Design Autom. Electr. Syst. 7 (1) (2002)
Meenakshi Kaul, Ranga Vemuri
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. J. VLSI Signal Process. 24 (2-3) (2000)
Meenakshi Kaul, Ranga Vemuri
Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures. IPPS/SPDP Workshops (1999)
Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. DAC (1999)
Meenakshi Kaul, Ranga Vemuri
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. DATE (1999)
Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. IPPS/SPDP Workshops (1998)
Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri
An Effective Design System for Dynamically Reconfigurable Architectures. FCCM (1998)
Meenakshi Kaul, Ranga Vemuri
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. DATE (1998)