Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths.
Stefan NikolicGrace ZgheibPaolo IennePublished in: FPL (2020)
Keyphrases
- shortest path
- path selection
- multiple paths
- routing algorithm
- data driven
- high speed
- real time
- field programmable gate array
- real time image processing
- ad hoc networks
- hardware implementation
- wavelength division multiplexing
- routing protocol
- network topology
- network topologies
- interconnection networks
- hardware architectures
- systolic array
- link failure
- verilog hdl
- hardware architecture
- wireless ad hoc networks
- hardware design
- routing problem
- multipath
- network traffic