A flexible DSP block to enhance FPGA arithmetic performance.
Hadi Parandeh-AfsharAlessandro CevreroPanagiotis AthanasopoulosPhilip BriskYusuf LeblebiciPaolo IennePublished in: FPT (2009)
Keyphrases
- verilog hdl
- signal processing
- real time image processing
- high speed
- digital signal processing
- systolic array
- digital signal
- hardware implementation
- real time
- field programmable gate array
- digital signal processor
- software implementation
- hardware design
- floating point
- data flow
- pattern recognition
- pipelined architecture
- digital signal processors
- learning algorithm
- block matching
- parallel architecture
- low power
- fpga implementation
- lightweight
- image processing