Resve A. Saleh

Publication Activity (10 Years)

Years Active: 1988-2022
Publications (10 Years): 4

Top Topics

Risk Minimization

Quantile Regression

Machine Learning

Top Venues

Publications

Resve A. Saleh, A. K. Md. Ehsanes Saleh
Statistical Properties of the log-cosh Loss Function Used in Machine Learning. CoRR (2022)
Sohaib Majzoub, Resve A. Saleh, Mottaqiallah Taouil, Said Hamdioui, Mohamed Bamakhrama
Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning. IEEE Access 10 (2022)
Resve A. Saleh, A. K. Md. Ehsanes Saleh
Solution to the Non-Monotonicity and Crossing Problems in Quantile Regression. CoRR (2021)
Sohaib Majzoub, Resve A. Saleh, Imran Ashraf, Mottaqiallah Taouil, Said Hamdioui
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era. IEEE Access 7 (2019)
Jeffrey G. Mueller, Resve A. Saleh
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. IEEE Trans. Very Large Scale Integr. Syst. 19 (6) (2011)
Tatsuya Koyagi, Sohaib Majzoub, Masahiro Fukui, Resve A. Saleh
RTL delay macro-modeling with Vt and Vdd variability. IDT (2011)
Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. SoC (2009)
Sohaib Majzoub, Resve A. Saleh, Rabab K. Ward
PVT variation impact on voltage island formation in MPSoC design. ISQED (2009)
Xiongfei Meng, Resve A. Saleh
An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs. IEEE J. Solid State Circuits 44 (2) (2009)
Xiongfei Meng, Resve A. Saleh
Active decap design considerations for optimal supply noise reduction. ISQED (2009)
Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton
Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC (2009)
Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC (2009)
Dipanjan Sengupta, Resve A. Saleh
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (3) (2009)
Uthman Alsaiari, Resve A. Saleh
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. ISQED (2008)
Jeff Mueller, Resve A. Saleh
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. ISQED (2008)
Dipanjan Sengupta, Resve A. Saleh
Supply voltage selection in Voltage Island based SoC design. SoCC (2008)
Zahra Sadat Ebadi, Resve A. Saleh
A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. ISQED (2008)
Peter Hallschmid, Resve A. Saleh
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh
Delay macromodeling and estimation for RTL. ISCAS (2008)
Xiongfei Meng, Resve A. Saleh, Karim Arabi
Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 16 (11) (2008)
Jeff Mueller, Resve A. Saleh
Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. VLSI Design (2008)
Zahra Sadat Ebadi, Resve A. Saleh
Adaptive Compensation of RF Front-End Nonidealities in Direct Conversion Receivers. IEEE Trans. Circuits Syst. II Express Briefs (4) (2008)
Dipanjan Sengupta, Resve A. Saleh
Application-driven floorplan-aware voltage island design. DAC (2008)
Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande
Testing Network-on-Chip Communication Fabrics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (12) (2007)
Amit Kedia, Resve A. Saleh
Power Reduction of On-Chip Serial Links. ISCAS (2007)
Karim Arabi, Resve A. Saleh, Xiongfei Meng
Power Supply Noise in SoCs: Metrics, Management, and Measurement. IEEE Des. Test Comput. 24 (3) (2007)
Peter Hallschmid, Resve A. Saleh
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. DAC (2007)
Uthman Alsaiari, Resve A. Saleh
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. ISQED (2007)
Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve A. Saleh, André Ivanov
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. Integr. 40 (2) (2007)
Resve A. Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki
DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? ISQED (2007)
Dipanjan Sengupta, Resve A. Saleh
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (1) (2007)
Xiongfei Meng, Karim Arabi, Resve A. Saleh
A Novel Active Decoupling Capacitor Design in 90nm CMOS. ISCAS (2007)
Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh
Essential Fault-Tolerance Metrics for NoC Infrastructures. IOLTS (2007)
Victor O. Aken'Ova, Resve A. Saleh
A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. ISVLSI (2006)
Xiongfei Meng, Resve A. Saleh, Karim Arabi
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. ISQED (2006)
Uthman Alsaiari, Resve A. Saleh
Testable and self-repairable structured logic design. ISCAS (2006)
Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh
A high-speed low-energy dynamic PLA using an input-isolation scheme. ISCAS (2006)
Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov
System-on-Chip: Reuse and Integration. Proc. IEEE 94 (6) (2006)
Zahra Sadat Ebadi, Shahriar Mirabbasi, Resve A. Saleh
The application of complex quantized feedback in integrated wireless receivers. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2006)
Peter Hallschmid, Resve A. Saleh
Fast Configuration of an Energy-Efficient Branch Predictor. ISVLSI (2006)
Resve A. Saleh
An approach that will NoC your SoCs off! IEEE Des. Test Comput. 22 (5) (2005)
Victor O. Aken'Ova, Guy Lemieux, Resve A. Saleh
An improved "soft" eFPGA design and implementation strategy. CICC (2005)
Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. IEEE Trans. Computers 54 (8) (2005)
Dipanjan Sengupta, Resve A. Saleh
Power-Delay Metrics Revisited for 90nm CMOS Technology. ISQED (2005)
Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
Design, Synthesis, and Test of Networks on Chips. IEEE Des. Test Comput. 22 (5) (2005)
James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh
SoC implementation issues for synthesizable embedded programmable logic cores. CICC (2003)
Stephan Shang, Shahriar Mirabbasi, Resve A. Saleh
A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. ISCAS (1) (2003)
Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov
Analog IP design flow for SoC applications. ISCAS (4) (2003)
Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama
Trends in Low Power Digital System-on-Chip Designs (invited). ISQED (2002)
Mohsen Nahvi, André Ivanov, Resve A. Saleh
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. ITC (2002)
Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser
Clock skew verification in the presence of IR-drop in the powerdistribution network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (6) (2000)
Resve A. Saleh, David Overhauser, Sandy Taylor
Full-chip verification of UDSM designs. ICCAD (1998)
Resve A. Saleh, Brian A. A. Antao, Jaidip Singh
Multilevel and mixed-domain simulation of analog circuits and systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (1) (1996)
Jeffrey G. Mueller, Brian A. A. Antao, Resve A. Saleh
A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (7) (1996)
Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
Improving Parallel Circuit Simulation Using High-Level Waveforms. ISCAS (1995)
Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
Improving the performance of parallel relaxation-based circuit simulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (11) (1993)
Eugene Z. Xia, Resve A. Saleh
Parallel waveform-Newton algorithms for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (4) (1992)
Yun-Cheng Ju, Resve A. Saleh
Incremental Circuit Simulation Using Waveform Relaxation. DAC (1992)
Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh
Exact Evaluation of Diagnostic Test Resolution. DAC (1992)
Yun-Cheng Ju, Resve A. Saleh
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. DAC (1991)
Jaidip Singh, Resve A. Saleh
iMACSIM: A Program for Multi-Level Analog Circuit Simulation. ICCAD (1991)
Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh
Consistency checking and optimization of macromodels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (8) (1991)
Yun-Cheng Ju, Resve A. Saleh
Identification of Viable Paths Using Binary Decision Diagrams. ICCD (1991)
Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
Parallel Event-Driven Waveform Relaxation. ICCD (1991)
Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh
Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. ICCAD (1990)
Resve A. Saleh, Jacob K. White
Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (9) (1990)
Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh
Parallel Circuit Simulation Using Hierarchical Relaxation. DAC (1990)
Resve A. Saleh, A. Richard Newton
The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (12) (1989)
Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh
Compaction of ATPG-generated test sequences for sequential circuits. ICCAD (1988)