Thomas M. Niermann

Publication Activity (10 Years)

Years Active: 1988-1997
Publications (10 Years): 0

Publications

Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
A genetic algorithm framework for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (9) (1997)
Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann
Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC (1994)
Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
Test compaction for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (2) (1992)
Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (2) (1992)
Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel
Methods for Reducing Events in Sequential Circuit Fault Simulation. ICCAD (1991)
Thomas M. Niermann, Janak H. Patel
HITEC: a test generation package for sequential circuits. EURO-DAC (1991)
Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. DAC (1990)
Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh
Compaction of ATPG-generated test sequences for sequential circuits. ICCAD (1988)