Rabindra K. Roy

Publication Activity (10 Years)

Years Active: 1988-2000
Publications (10 Years): 0

Publications

T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson
EDA challenges facing future microprocessor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee
Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. J. Electron. Test. 14 (3) (1999)
Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy
Characterizing Individual Gate Power Sensitivity in Low Power Design. VLSI Design (1999)
Sujit Dey, Anand Raghunathan, Rabindra K. Roy
Considering Testability during High-level Design (Embedded Tutorial). ASP-DAC (1998)
Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis. J. VLSI Signal Process. 18 (1) (1998)
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design (1998)
Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee
Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. VLSI Design (1998)
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. 13 (2) (1998)
Abhijit Chatterjee, Rabindra K. Roy
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization. IEEE Trans. Computers 46 (11) (1997)
Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy
T5: Low-Power Design. VLSI Design (1997)
Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy
Impact of Partial Reset on Fault Independent Testing and BIST. VLSI Design (1997)
Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy
Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design (1996)
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
Synthesis of initializable asynchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. 4 (2) (1996)
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar
Initialization issues in asynchronous circuit synthesis. J. Electron. Test. 9 (3) (1996)
Tam-Anh Chu, Rabindra K. Roy
Guest Editors' Introduction: More Practical Asynchronous Design. IEEE Des. Test Comput. 12 (1) (1995)
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (9) (1995)
Rabindra K. Roy
Advantages of High-Level Test Synthesis over Design for Test. ITC (1995)
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
Synthesis-for-testability using transformations. ASP-DAC (1995)
Tam-Anh Chu, Rabindra K. Roy
Guest Editor's Introduction: Practical Asynchronous Design. IEEE Des. Test Comput. 11 (2) (1994)
Abhijit Chatterjee, Rabindra K. Roy
Design for diagnosability of linear digital filters using time-space expansion. VTS (1994)
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
Behavioral synthesis of low-cost partial scan designs for DSP applications. ICASSP (2) (1994)
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC (1994)
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. VTS (1994)
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
Synthesis of Initializable Asynchronous Circuits. VLSI Design (1994)
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD (1994)
Abhijit Chatterjee, Rabindra K. Roy
Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. VLSI Design (1994)
Abhijit Chatterjee, Rabindra K. Roy
Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. ICCD (1993)
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
Exploiting hardware sharing in high-level synthesis for partial scan optimization. ICCAD (1993)
Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting. VLSI Design (1993)
Abhijit Chatterjee, Rabindra K. Roy
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition. DAC (1993)
Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
Greedy hardware optimization for linear digital circuits using number splitting and refactorization. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD (1992)
Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu
Delay fault testing of iterative arithmetic arrays. VTS (1992)
Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
Test compaction for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (2) (1992)
Miron Abramovici, David T. Miller, Rabindra K. Roy
Dynamic redundancy identification in automatic test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (3) (1992)
Miron Abramovici, James J. Kulikowski, Rabindra K. Roy
The Best Flip-Flops to Scan. ITC (1991)
Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors. Digit. Signal Process. 1 (4) (1991)
Miron Abramovici, David T. Miller, Rabindra K. Roy
Dynamic redundancy identification in automatic test generation. ICCAD (1989)
Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
Fault Simulation in a Distributed Environment. DAC (1988)
Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh
Compaction of ATPG-generated test sequences for sequential circuits. ICCAD (1988)